
(12)
The performance of the converter will vary depending on the
selected K value (See
Table 1). For this example, 3 was cho-
sen as the K factor to minimize the power loss in sense
resistor R
S and the cross-talk between channels. Crosstalk
between the two regulators under certain conditions may be
observed on the output as switch jitter.
The maximum output current capability (I
OUT(MAX)) should be
20~50% higher than the required output current, (8A at
V
OUT1) to account for tolerances and ripple current. For this
example, 130% of 8A was chosen (10.4A). The current sense
resistor value can be calculated as:
(13)
(14)
Where V
CS(TH) is the current limit threshold voltage (120mV).
A value of 8m
was chosen for R
S. The sense resistor must
be rated to handle the power dissipation at maximum input
voltage when current flows through the free-wheel MOSFET
for the majority of the PWM cycle. The maximum power dis-
sipation of R
S can be calculated:
(15)
(16)
During output short condition, the worst case peak inductor
current is limited to:
(17)
(18)
Where t
ON(MIN) is the minimum HO on-time which is nominally
100ns. The chosen inductor must be evaluated for this con-
dition, especially at elevated temperature where the satura-
tion current rating of the inductor may drop significantly. At the
maximum input voltage with a shorted output, the valley cur-
rent must fall below V
CS(TH) / RS before the high-side MOSFET
is allowed to turn on.
RAMP RESISTOR AND RAMP CAPACITOR
The value of ramp capacitor (C
RAMP) should be less than 2nF
to allow full discharge between cycles by the discharge switch
internal to the LM25119. A good quality, thermally stable ce-
ramic capacitor with 5% or less tolerance is recommended.
For this design the value of C
RAMP was set at the standard
capacitor value of 820pF. With the inductor, sense resistor
and the K factor selected, the value of the ramp resistor
(R
RAMP) can be calculated as:
(19)
(20)
The standard value of 34k
was selected.
OUTPUT CAPACITORS
The output capacitors smooth the inductor ripple current and
provide a source of charge during transient loading condi-
tions. For this design example, a 680F electrolytic capacitor
with 10m
ESR was selected as the main output capacitor.
The fundamental component of the output ripple voltage is
approximated as:
(21)
(22)
(23)
Two 22F low ERS / ESL ceramic capacitors are placed in
parallel with the 680F electrolytic capacitor, to further reduce
the output voltage ripple and spikes.
TABLE 1. Performance Variation by K Factor
K < 1
1 <— K —> 3
K > 3
Cross Talk
Sub-harmonic
oscillation may occur
Higher
Lower
Introduces
additional pole near
cross-over
frequency
Peak Inductor Current with Short Output
Condition
Lower
Higher
Inductor Size
Smaller
Larger
Power Dissipation of Rs
Higher
Lower
Efficiency
Lower
Higher
www.national.com
16
LM25119