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参数资料
| 型号： | LM25119PSQX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC32 |
| 封装： | 5 X 5 MM, LLP-32 |
| 文件页数： | 13/24页 |
| 文件大小： | 694K |
| 代理商： | LM25119PSQX |
error amplifier transfer function. This pole must be well be-
yond the loop crossover frequency. A good approximation of
the location of the pole added by C
HF is: fP2 = fZEA x CCOMP /
C
HF. The value of CHF was selected as 100pF for the design
example.
Miscellaneous Functions
EN2 is left floating which allows channel2 to always remain
enabled. If EN2 is pulled below 2V, channel2 is disabled.
The DEMB pin is left floating since this design uses diode
emulation. For fully synchronous (continuous conduction) op-
eration, connect the DEMB to a voltage greater than 2.6V.
VCCDIS is left floating to enable the internal VCC regulators.
To disable the internal VCC regulators, connect this pin to a
voltage greater than 1.25V.
Interleaved Operation
Interleaved operation can offer many advantages in single
output, high current applications. The output power path is
split between two identical channels reducing the current in
each channel by one-half. Ripple current reduction in the out-
put capacitors is reduced significantly since each channel
operates 180 degrees out of phase from the other. Ripple re-
duction is greatest at 50% duty cycle and decreases as the
duty cycle varies away from 50%.
Refer to Figure 12 to estimate the ripple current reduction.
Also, the effective ripple in the input and output capacitors
occurs at twice the frequency of a single channel design due
to the combining of the two channels. All of these factors are
advantageous in managing the higher currents and their ef-
fects in a high power design.
30126219
FIGURE 12. Cancellation Factor vs. Duty Cycle for Output
Capacitor
To begin an interleaved design, use the previous equations
in this datasheet to first calculate the required value of com-
ponents using one-half the current in the output power path.
The Attenuation Factor in Figure 12 is the ratio of the output
capacitor ripple to the inductor ripple vs. duty cycle. The in-
ductor ripple used in this calculation is the ripple in either
inductor in a two phase design, not the ripple calculated for a
single phase design of the same output power. It can be ob-
served that operation around 50% duty cycle results in almost
complete ripple attenuation in the output capacitor. Figure
12 can be used to calculate the amount of ripple attenuation
in the output capacitors.
30126220
FIGURE 13. Normalized Input Capacitor RMS Ripple
Current vs. Duty Cycle
Figure 13 illustrates the ripple current reduction in the input
capacitors due to interleaving. As with the output capacitors,
there is near perfect ripple reduction near 50% duty cycle.
This plot can be used to calculate the ripple in the input ca-
pacitors at any duty cycle. In designs with large duty cycle
swings, use the worst case ripple reduction for the design.
To configure the LM25119 for interleaved operation, connect
COMP1 and COMP2 pins together at the IC. Connecting the
FB2 pin to VCC2 pin will disable the channel2 error amplifier
with a high output impedance at COMP2. Connect the com-
pensation network between FB1 and the common COMP
pins. Connect the two power stages together at the output
along with the duty cycle range to determine the amount of
output and input capacitor ripple reduction. Frequently more
capacitance than necessary is used in a design just to meet
ESR requirements. Reducing the capacitance based solely
on ripple reduction graphs alone may violate this requirement.
In the LM25119 evaluation board (schematic shown in Figure
14) interleaved operation can be enabled by shorting both
outputs together (with identical components in the power
train), and using zero ohm resistors for R22 and R21. This
shorts VCC2 to FB2 and COMP2 to COMP1 respectively. Al-
so the channel2 feedback network C14, R6, and C15 should
be removed. The easy re-configuration between two channel
and single channel operation will allow insight into the benefits
of interleaved operation.
www.national.com
20
LM25119
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LM25119PSQX/NOPB | 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| LM25119QPSQ/NOPB | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC REG CTRLR BUCK PWM CM 32-LLP 制造商:Texas Instruments 功能描述:LM25119QPSQ/NOPB |
| LM25119QPSQX/NOPB | 制造商:Texas Instruments 功能描述:IC REG CTRLR BUCK PWM CM 32-LLP 制造商:Texas Instruments 功能描述:Dual Synchronous Buck Controller |
| LM2512 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Mobile Pixel Link Level 0, 24-Bit RGB Display Interface Serializer with Dithering and Look Up Table Option |
| LM-2512 | 制造商:ROHM 制造商全称:Rohm 功能描述:16 x 32 matrix display |
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