参数资料
型号: LM5051MAX/NOPB
厂商: National Semiconductor
文件页数: 2/23页
文件大小: 0K
描述: IC ORING FET CTRLR 8SOIC
标准包装: 2,500
应用: 冗余电源
FET 型: N 沟道
输出数: 1
内部开关:
电源电压: 36 V ~ 100 V
电流 - 电源: 400µA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
SNVS702D – OCTOBER 2011 – REVISED MARCH 2013
LINE
VCC
LM5051
PS1
INN GATE INP/VSS
D
S
PS2
LINE
LM5051
VCC
R LOAD
INN GATE
D
INP/VSS
S
Figure 2. Typical Redundant Supply Configuration
Connection Diagram
Top View
LINE 1
VCC 2
OFF 3
nFGD 4
8 GATE
7 INP/VSS
6 INN
5 INP/VSS
Device Pin 5 (INP) is internally connected to Device Pin 7 (VSS)
Figure 3. LM5051MA
8-Lead SOIC D Package
PIN DESCRIPTIONS
Pin #
1
2
3
4
5
6
7
Name
LINE
VCC
OFF
nFGD
INP/VSS
INN
INP/VSS
Function
Power supply pin to bias the internal 12V zener shunt regulator at the
VCC pin through an internal 50 k ? (typical) series resistor. See the
Connection to the internal 12V zener shunt voltage regulator. Bypass
this pin with minimum 0.1 μ F capacitor to the VSS pin. This pin can be
biased via an external resistor rather than via the internal resistor from
the LINE pin (pin 1). See the APPLICATION INFORMATION section.
FET Test Mode control input. Logic low or open state at the OFF pin
will deactivate the FET Test Mode and allow normal operation. A logic
high state at the OFF pin will pull the GATE pin low and turn off the
external MOSFET. If the body diode forward voltage of the MOSFET
(from source to drain) is greater than 260mV the nFGD pin will indicate
that the MOSFET is not shorted by pulling to the active low state.
Open drain output for the FET Test circuit. An active low state on nFGD
indicates that the forward voltage (from source to drain) of the external
MOSFET is greater than 260 mV typical. The nFGD pin requires an
external pull-up resistor to a voltage not higher than VSS + 5.5V.
See device Pin 7.
Voltage sense connection to the external MOSFET Drain pin
Internally connected to device Pin 5. Negative supply voltage
connection and MOSFET voltage sense connected to the external
MOSFET common source connection. All device voltages and currents
are referenced to this pin, unless otherwise stated. See the INP/VSS
PINS section.
2
Product Folder Links: LM5051
Copyright ? 2011–2013, Texas Instruments Incorporated
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