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| 型号： | LM5051MAX/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 5/23页 |
| 文件大小： | 0K |
| 描述： | IC ORING FET CTRLR 8SOIC |
| 标准包装： | 2,500 |
| 应用： | 冗余电源 |
| FET 型： | N 沟道 |
| 输出数： | 1 |
| 内部开关： | 无 |
| 电源电压： | 36 V ~ 100 V |
| 电流 - 电源： | 400µA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
SNVS702D – OCTOBER 2011 – REVISED MARCH 2013
Electrical Characteristics (continued)
Limits in standard type are for T J = 25°C only; limits in boldface type apply over the operating junction temperature (T J )
range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at T J = 25°C, and are provided for reference purposes only. Unless
otherwise stated all conditions and measurements are referenced to device pin 7 (INP/VSS), and the following conditions
apply: V LINE = 48.0V, V INN = -150 mV, V OFF = 0.0V, C GATE = 47 nF, C VCC = 0.1 μF, and T J = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FET Test Comparator
V SD(TST)
FET Test Threshold Voltage
V INP - V INN
V OFF = 5.0V
V INN/VSS going negative from
V INP until nFGD pin goes Hi-Z
-360
-260
-183
mV
V OFF = 5.0V
Δ V SD(TST)
FET Test Threshold Voltage Hysteresis
V INN going positve from
V SDT(ST) until nFGD pin goes
-
6.5
-
mV
Lo-Z
nFGD Pin
nFGD VOL
nFGD IOL
nFGD Output Low Voltage
nFGD Output = On
nFGD Output Leakage Current
nFGD Output = Off
V OFF = 5V
I nFGD = 1mA Sinking
V OFF = 0V
V nFGD = 5.0V
-
-
285
0.01
450
0.7
mV
μA
V SD(REG)
0.0 mV
? V SD(REV)
V SD(REV)
V GATE
0.0V
Figure 4. V SD(REV) Threshold Definitions
0.0 mV
? V SD(TST)
V SD(TST)
V nFGD
0.0V
Figure 5. V SD(TST) Threshold Definitions
Copyright ? 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM5051
5
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