参数资料
型号: LPC2294JBD144,551
厂商: NXP Semiconductors
文件页数: 3/54页
文件大小: 0K
描述: IC ARM7 MCU FLASH 256K 144-LQFP
标准包装: 60
系列: LPC2200
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 60MHz
连通性: CAN,EBI/EMI,I²C,Microwire,SPI,SSI,SSP,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 112
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 144-LQFP
包装: 托盘
配用: OM10091-ND - KIT DEV PHYCORE-ARM7/LPC2220
568-1757-ND - BOARD EVAL FOR LPC220X ARM MCU
其它名称: 568-1898
935275728551
LPC2294JBD144-S
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
11 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
P1[25]/EXTIN0
K8[7]
I
EXTIN0 — External Trigger Input. Standard I/O with internal
pull-up.
P1[26]/RTCK
N6[7]
I/O
RTCK — Returned Test Clock output. Extra signal added to
the JTAG port. Assists debugger synchronization when
processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins
P1[31:26] to operate as Debug port after reset.
P1[27]/TDO
144[7]
B2[7]
O
TDO — Test Data out for JTAG interface.
P1[28]/TDI
140[7]
A3[7]
I
TDI — Test Data in for JTAG interface.
P1[29]/TCK
126[7]
A7[7]
I
TCK — Test Clock for JTAG interface. This clock must be
slower than 16 of the CPU clock (CCLK) for the JTAG
interface to operate.
P1[30]/TMS
113[7]
I
TMS — Test Mode Select for JTAG interface.
P1[31]/TRST
M4[7]
I
TRST — Test Reset for JTAG interface.
P2[0] to P2[31]
I/O
Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 2 pins
depends upon the pin function selected via the Pin Connect
Block.
P2[0]/D0
I/O
D0 — External memory data line 0.
P2[1]/D1
105[7]
I/O
D1 — External memory data line 1.
P2[2]/D2
106[7]
I/O
D2 — External memory data line 2.
P2[3]/D3
108[7]
I/O
D3 — External memory data line 3.
P2[4]/D4
109[7]
I/O
D4 — External memory data line 4.
P2[5]/D5
114[7]
I/O
D5 — External memory data line 5.
P2[6]/D6
115[7]
I/O
D6 — External memory data line 6.
P2[7]/D7
116[7]
I/O
D7 — External memory data line 7.
P2[8]/D8
117[7]
D9[7]
I/O
D8 — External memory data line 8.
P2[9]/D9
118[7]
C9[7]
I/O
D9 — External memory data line 9.
P2[10]/D10
120[7]
A9[7]
I/O
D10 — External memory data line 10.
P2[11]/D11
124[7]
A8[7]
I/O
D11 — External memory data line 11.
P2[12]/D12
125[7]
B7[7]
I/O
D12 — External memory data line 12.
P2[13]/D13
127[7]
C7[7]
I/O
D13 — External memory data line 13.
P2[14]/D14
129[7]
A6[7]
I/O
D14 — External memory data line 14.
P2[15]/D15
130[7]
B6[7]
I/O
D15 — External memory data line 15.
P2[16]/D16
131[7]
C6[7]
I/O
D16 — External memory data line 16.
P2[17]/D17
132[7]
D6[7]
I/O
D17 — External memory data line 17.
P2[18]/D18
133[7]
A5[7]
I/O
D18 — External memory data line 18.
P2[19]/D19
134[7]
B5[7]
I/O
D19 — External memory data line 19.
P2[20]/D20
136[7]
D5[7]
I/O
D20 — External memory data line 20.
P2[21]/D21
137[7]
A4[7]
I/O
D21 — External memory data line 21.
P2[22]/D22
A1[7]
I/O
D22 — External memory data line 22.
P2[23]/D23
E3[7]
I/O
D23 — External memory data line 23.
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
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