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参数资料
| 型号： | LT1737IS#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO CM 16SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 125kHz |
| 占空比： | 90% |
| 电源电压： | 4.1 V ~ 20 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
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LT1737
OPERATIO
Enable Delay
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
former primary side voltage waveform approximately rep-
resents the output voltage. This is partly due to finite rise
time on the MOSFET drain node, but more importantly,
due to transformer leakage inductance. The latter causes
a voltage spike on the primary side not directly related to
output voltage. (Some time is also required for internal
settling of the feedback amplifier circuitry.)
In order to maintain immunity to these phenomena, a fixed
delay is introduced between the switch turnoff command
and the enabling of the feedback amplifier. This is termed
enable delay. In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Application Infor-
mation for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB referred) to a fixed reference, nominally 80%
of V BG . When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodates both continuous and discontinuous mode
operation.
Minimum Enable Time
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time.” This prevents lockup, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the V C node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
the low load level at which output voltage regulation is lost.
See Applications Information for details.
Effects of Variable Enable Period
It should now be clear that the flyback amplifier is enabled
during only a portion of the cycle time. This can vary from
the fixed “minimum enable time” described to a maximum
of roughly the “off” switch time minus the enable delay
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and V C node slew rate.
LOAD COMPENSATION THEORY
The LT1737 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
T1
V IN
I M
R1
FB
+
M1
R2
LOAD
Q1 Q2
V BG
Q3
A1
–
R3
50k
I SENSE
COMP I
I M
R OCMP
R CMPC
R SENSE
1737 F01
Figure 1. Load Compensation Diagram
1737fa
10
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