参数资料
型号: LT3837EFE#TRPBF
厂商: Linear Technology
文件页数: 21/28页
文件大小: 0K
描述: IC REG CTRLR FLYBK ISO 16-TSSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 250kHz
占空比: 88%
电源电压: 4.5 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 带卷 (TR)
LT3837
APPLICATIONS INFORMATION
? ? 1 + MIN ?
I PK =
I RMSPRI =
I RMSSEC =
Iftheoutputloadcurrentisrelativelyconstant,thefeedback
resistive divider is used to compensate for these losses.
Otherwise, use the LT3837 load compensation circuitry
(see Load Compensation).
If multiple output windings are used, the flyback winding
will have a signal that represents an amalgamation of all
these windings impedances. Take care that you examine
worst-case loading conditions when tweaking the volt-
ages.
Power MOSFET Selection
The power MOSFETs are selected primarily on the criteria of
on-resistance R DS(ON) , input capacitance, drain-to-source
breakdown voltage (BV DSS ), maximum gate voltage (VGS)
and maximum drain current (I D(MAX) ).
For the primary-side power MOSFET, the peak current
is:
I OUT ? X ?
1–DC MAX ? 2 ?
where X is peak-to-peak current ratio as defined earlier.
Choose the primary side MOSFET R DS(ON) at the nominal
gate drive voltage (7.5V). The secondary side MOSFET
gate drive voltage depends on the gate drive method.
Primary side power MOSFET RMS current is given by:
P IN
V IN(MIN) DC MAX
For each secondary-side power MOSFET RMS current is
given by:
I OUT
1–DC MAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET may operate at high V DS , a
transition power loss term is included for accuracy. C MILLER
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
C MILLER is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 6).
For each secondary-side power MOSFET, the peak cur-
rent is:
V GS
a
MILLER EFFECT
b
? ? 1 + MIN ?
Q A Q B
I PK =
I OUT
1–DC MAX
? 2 ?
? X ?
3825 F06
GATE CHARGE (Q G )
Figure 6. Gate Charge Curve
BV DSS ≥ I PK
+ V IN(MAX) +
C MILLER =
Selectaprimary-sidepowerMOSFETwithaB VDSS greater
than:
L LKG V OUT(MAX)
C P N SP
where N SP reflects the turns ratio of that secondary-to-pri-
mary winding. L LKG is the primary-side leakage inductance
and C P is the primary-side capacitance (mostly from the
C OSS of the primary-side power MOSFET). A snubber
may be added to reduce the leakage inductance spike as
discussed earlier.
The flat portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops.
The Miller capacitance is computed as:
Q B – Q A
V DS
The curve is done for a given V DS . The Miller capacitance
for different V DS voltages are estimated by multiplying the
computed C MILLER by the ratio of the application V DS to
the curve specified V DS .
For each secondary-side power MOSFET, the BV DSS should
be greater than:
BV DSS ≥ V OUT + V IN(MAX) ? N SP
3837fd
21
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