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参数资料
| 型号： | LT3837EFE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO 16-TSSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 占空比： | 88% |
| 电源电压： | 4.5 V ~ 20 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
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LT3837
APPLICATIONS INFORMATION
Continuing our example, the output capacitor needs:
PRIMARY
CURRENT
I PRI
ESR COUT ≤ 1% ?
3.3V ? ( 1– 52.4% )
10A
= 1.6m ?
C OUT ≥
10A
1% ? 3.3 ? 200kHz
= 1515 μ F
SECONDARY
CURRENT
I PRI
N
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
OUTPUT VOLTAGE
RIPPLE WAVEFORM
? V COUT
? V ESR
RINGING
DUE TO ESL
3825 F07
Most capacitor ripple current ratings are based on 2000
hour life. This makes it advisable to derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
V OUT
V OUT ? ( 1–DC MAX )
ESR COUT ≤ 1% ?
C OUT ≥
C OUT
C OUT2
SECONDARY 47μF R LOAD
WINDING
× 3
Figure7.TypicalFlybackConverterWaveforms
ESR and ESL along with bulk capacitance directly affect
the output voltage ripple. The waveforms for a typical
flyback converter are illustrated in Figure 7.
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose
of simplicity we will choose 2% for the maximum output
ripple, divided equally between the ESR step and the
charging/discharging ?V. This percentage ripple changes,
depending on the requirements of the application. You can
modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
I OUT
The other 1% is due to the bulk C component, so use:
I OUT
1% ? V OUT ? f OSC
In many applications the output capacitor is created from
multiple capacitors to achieve desired voltage ripple, reli-
ability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
One way to reduce cost and improve output ripple is to
use a simple LC filter. Figure 8 shows an example of the
filter.
L1
0.1μH
FROM C1
470μF 1μF
3837 F08
Figure 8
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guide lines. Start with a C OUT 1/4 the size of the nonfilter
solution. Make C1 1/4 of C OUT to make the second filter
pole independent of C OUT . The smaller C1 may be best
implemented with multiple ceramic capacitors. Make L1
smaller than the output inductance of the transformer. In
general, a 0.1μH filter inductor is sufficient. Add a small
ceramic capacitor (C OUT2 ) for high frequency noise on
V OUT . For those interested in more details refer to “Sec-
ond-Stage LC Filter Design,” Ridley, Switching Power
Magazine, July 2000, p8-10.
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component
parasitics. LTC SwitcherCAD? is a terrific free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
significantly impact ripple. Refer to the PC Board Layout
section for more details.
SwitcherCAD is a trademark of Linear Technology Corporation.
3837fd
23
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| LT3837IFE#PBF | 功能描述:IC REG CTRLR FLYBK ISO 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
| LT3837IFE#TRPBF | 功能描述:IC REG CTRLR FLYBK ISO 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
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