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参数资料
| 型号： | LTC1149CS-5#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 16-SOIC |
| 标准包装： | 50 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 占空比： | 100% |
| 电源电压： | 最高 48V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
LTC1149
LTC1149-3.3/LTC1149-5
PI FU CTIO S
PGATE (Pin 1): Level-Shifted Gate Drive Signal for Top
P-Channel MOSFET. The voltage swing at Pin 1 is from V IN
to V IN – V CC .
V IN (Pin 2): Main Supply Input Pin.
V CC (Pin 3): Output Pin of Low Dropout 10V Regulator. Pin
3 is not protected against DC short circuits.
PDRIVE (Pin 4): High Current Gate Drive for Top
P-Channel MOSFET. The voltage swing at Pin 4 is from V CC
to ground.
V CC (Pin 5): Regulated 10V Input for Driver and Control
Supplies. Must be closely decoupled to power ground.
C T (Pin 6): External capacitor C T from Pin 6 to ground sets
the operating frequency. (The frequency is also dependent
on the ratio V OUT /V IN .)
I TH (Pin 7): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 7 voltage.
SENSE – (Pin 8): Connects to internal resistive divider
which sets the output voltage in LTC1149-3.3 and
LTC1149-5 versions. Pin 8 is also the (–) input for the
current comparator.
SENSE + (Pin 9): The (+) Input for the Current Comparator.
A built-in offset between Pins 8 and 9 in conjunction with
R SENSE sets the current trip threshold.
SHDN1/V FB (Pin 10): In fixed output voltage versions, Pin
10 serves as a shutdown pin for the control circuitry only
(V CC is not affected). Taking Pin 10 of the LTC1149-3.3 or
LTC1149-5 high holds both MOSFETs off. Must be at
ground potential for normal operation.
For the LTC1149 adjustable version, Pin 10 serves as the
feedback pin from an external resistive divider used to set
the output voltage.
SGND (Pin 11): Small-Signal Ground. Must be routed
separately from other grounds to the (–) terminal of C OUT .
PGND (Pin 12): Driver Power Ground. Connects to source
of N-channel MOSFET and the (–) terminal of C IN .
NGATE (Pin 13): High Current Drive for Bottom
N-channel MOSFET. The voltage swing at Pin 13 is from
ground to V CC .
RGND (Pin 14): Low Dropout Regulator Ground. Con-
nects to power ground.
SHDN2 (Pin 15): Master Shutdown Pin. Taking Pin 15
high shuts down V CC and all control circuitry; requires a
logic signal with t r , t f < 1 μ s.
CAP (Pin 16): Charge Compensation Pin. A capacitor from
Pin 16 to V CC provides the charge required by the P-drive
level-shift capacitor during supply transitions. The Pin 16
capacitor must be larger than the Pin 4 capacitor.
OPERATIO
(Refer to Functional Diagram)
The LTC1149 series uses a current mode, constant off-
time architecture to synchronously switch an external pair
of complementary power MOSFETs. Operating frequency
is set by an external capacitor at the timing capacitor,
Pin 6.
The output voltage is sensed either by an internal voltage
divider connected to SENSE – , Pin 8 (LTC1149-3.3 and
LTC1149-5) or an external divider returned to V FB Pin 10
(LTC1149). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference
voltage of 1.25V. To optimize efficiency, the LTC1149
series automatically switches between two modes of
operation, burst and continuous. The voltage comparator
is the primary control element for Burst Mode operation,
while the gain block controls the output voltage in continu-
ous mode.
A low dropout 10V regulator provides the operating volt-
age V CC for the MOSFET drivers and control circuitry. The
driver outputs at Pins 4 and 13 are referenced to ground,
which fulfills the N-channel MOSFET gate drive require-
ment. The P-channel gate drive at Pin 1 must be refer-
enced to the main supply input V IN , which is accomplished
by level-shifting the Pin 4 signal via an internal 500k
resistor and external capacitor.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 8 and 9
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the PGATE output is switched to V IN ,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 6 is now allowed to discharge at a rate
determined by the off-time controller. The discharge
5
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