参数资料
型号: LTC2215CUP
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封装: 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64
文件页数: 11/36页
文件大小: 1703K
代理商: LTC2215CUP
LTC2216/LTC2215
19
22165f
For LVDS Mode. STANDARD or LOW POWER
SENSE (Pin 1): Reference Mode Select and External Refer-
ence Input. Tie SENSE to VDD to select the internal 2.5V
bandgap reference. An external reference of 2.5V or 1.25V
may be used; both reference values will set a full-scale
ADC range of 2.75V.
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.
VCM (Pin 3): 1.575V Output. Optimum voltage for input
common mode. Must be bypassed to ground with a
minimum of 2.2μF. Ceramic chip capacitors are recom-
mended.
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
Bypass to GND with 1μF ceramic chip capacitors.
AIN+ (Pin 8): Positive Differential Analog Input.
AIN– (Pin 9): Negative Differential Analog Input.
ENC+ (Pin 12):
Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2k
Ω resistor. Output
data can be latched on the rising edge of ENC+.
ENC(Pin 13):
Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC.
Internally biased to 1.6V through a 6.2k
Ω resistor. By-
pass to ground with a 0.1μF capacitor for a single-ended
Encode signal.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are set in
high impedance state.
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of the data sheet for details
on dither operation.
D0/D0+ to D15/D15+ (Pins 21-30, 33-38, 41-48 and
51-58): LVDS Digital Outputs. All LVDS outputs require
differential 100
ΩterminationresistorsattheLVDSreceiver.
D15+/D15is the MSB.
OGND (Pins 31 and 50): Output Driver Ground.
OVDD (Pins 32 and 49): Positive Supply for the Output
Drivers. Bypass to ground with 0.1μF capacitor.
CLKOUT/CLKOUT+ (Pins 39 and 40):
LVDS Data Valid
0utput. Latch data on the rising edge of CLKOUT+, falling
edge of CLKOUT.
OF/OF+ (Pins 59 and 60):
Over/Under Flow Digital Output
OF is high when an over or under ow has occurred.
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demultiplexed CMOS mode. Connecting
LVDS to 2/3VDD selects Low Power LVDS mode. Connect-
ing LVDS to VDD selects Standard LVDS mode.
MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3VDDselects2’scomplement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 63): Digital Output Randomization Selection Pin.
RAND low results in normal operation. RAND high selects
D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The
output can be decoded by again applying an XOR operation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.
NC (Pin 64): Not Connected Internally. For pin compat-
ibility with the LTC2208 this pin should be connected to
GND or VDD as required. Otherwise no connection.
GND (Exposed Pad Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package must be sol-
dered to ground.
PIN FUNCTIONS
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