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参数资料
| 型号： | LTC2215CUP |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封装： | 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件页数： | 15/36页 |
| 文件大小： | 1703K |
| 代理商： | LTC2215CUP |
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LTC2216/LTC2215
22
22165f
CONVERTER OPERATION
TheLTC2216/LTC2215areCMOSpipelinedmultistepconvert-
ers with a low noise front-end. As shown in Figure 1, these
convertershavevepipelinedADCstages;asampledanalog
input will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2216/LTC2215 have two phases of operation, deter-
mined by the state of the differential ENC+/ENC– input pins.
For brevity, the text will refer to ENC+ greater than ENC– as
ENC high and ENC+ less than ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplied and
output by the residue amplier. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplier which
drives the rst pipelined ADC stage. The rst stage acquires
the output of the S/H amplier during the high phase of
ENC. When ENC goes back low, the rst stage produces
its residue which is acquired by the second stage. At the
same time, the input S/H goes back to acquiring the analog
input. When ENC goes high, the second stage produces
its residue which is acquired by the third stage. An identi-
cal process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fth
stage for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2216/
LTC2215 CMOS differential sample and hold. The differ-
ential analog inputs are sampled directly onto sampling
capacitors (CSAMPLE) through NMOS transistors. The
capacitors shown attached to each input (CPARASITIC) are
the summation of all other capacitance associated with
each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions for high to low, the inputs are reconnected to
Figure 2. Equivalent Input Circuit
VDD
LTC2216/LTC2215
AIN+
22165 F02
VDD
AIN–
ENC–
ENC+
1.6V
6k
VDD
1.6V
6k
RPARASITIC
3Ω
CSAMPLE
7.3pF
CSAMPLE
7.3pF
CPARASITIC
1.8pF
CPARASITIC
1.8pF
RPARASITIC
3Ω
RON
20Ω
RON
20Ω
APPLICATIONS INFORMATION
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2216CUP#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2216IUP#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2216IUP | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2216CUP | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2215IUP | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2215CUP#PBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 64-QFN |
| LTC2215CUP#TRPBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 64-QFN |
| LTC2215CUP-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Low Noise ADC |
| LTC2215CUP-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Low Noise ADC |
| LTC2215CUP-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Low Noise ADC |
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