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参数资料
| 型号： | LTC2215CUP |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封装： | 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件页数： | 19/36页 |
| 文件大小： | 1703K |
| 代理商： | LTC2215CUP |
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LTC2216/LTC2215
26
22165f
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2216/LTC2215 sample rate
is determined by droop affecting the sample and hold
circuits. The pipelined architecture of this ADC relies on
storing analog signals on small valued capacitors. Junc-
tion leakage will discharge the capacitors. The specied
minimum operating frequency for both the LTC2215 and
LTC2216 is 1Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2216/LTC2215 can operate in four digital output
modes: standard LVDS, low power LVDS, full rate CMOS,
and demultiplexed CMOS. The LVDS pin selects the mode
of operation. This pin has a four level logic input, centered
at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider
can be used to set the 1/3VDD and 2/3VDD logic levels.
Table 1 shows the logic states for the LVDS pin.
Table 1. LVDS Pin Function
LVDS
DIGITAL OUTPUT MODE
0V(GND)
Full-Rate CMOS
1/3VDD
Demultiplexed CMOS
2/3VDD
Low Power LVDS
VDD
LVDS
Digital Output Buffers (CMOS Modes)
Figure 11 shows an equivalent circuit for a single output
buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
buffer is powered by OVDD and OGND, isolated from the
ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to low voltages.
The internal resistor in series with the output makes the
output appear as 50
Ω to external circuitry and eliminates
the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2216/LTC2215 should drive a
minimum capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as the
22165 F11
ENC–
ENC+
3.3V
D0
Q0
MC100LVELT22
130Ω
83Ω
LTC2216/
LTC2215
Figure 11. ENC Drive Using a CMOS to PECL Translator
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2216 is 80Msps,
while the maximum encode rate for the LTC2215 is 65Msps.
For the ADCs to operate properly the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 5.94ns for the LTC2216 internal circuitry to have
enough settling time for proper operation. For the LTC2215,
each half cycle must be at least 7.31ns. Achieving a pre-
cise 50% duty cycle is easy with differential sinusoidal
drive using a transformer or using symmetric differential
logic such as PECL or LVDS. When using a single-ended
ENCODE signal asymmetric rise and fall times can result
in duty cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
Figure 10. Single-Ended ENC Drive,
Not Recommended for Low Jitter
22165 F10
ENC–
1.6V
VTHRESHOLD = 1.6V
ENC+
0.1μF
LTC2216/
LTC2215
APPLICATIONS INFORMATION
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2216CUP#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2216IUP#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2216IUP | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2216CUP | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2215IUP | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2215CUP#PBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 64-QFN |
| LTC2215CUP#TRPBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 64-QFN |
| LTC2215CUP-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Low Noise ADC |
| LTC2215CUP-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Low Noise ADC |
| LTC2215CUP-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Low Noise ADC |
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