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参数资料
| 型号： | LTC2215CUP |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封装： | 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件页数： | 16/36页 |
| 文件大小： | 1703K |
| 代理商： | LTC2215CUP |
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LTC2216/LTC2215
23
22165f
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specied performance. Each input should swing
±0.6875V for the 2.75V range, around a common mode
voltage of 1.575V. The VCM output pin (Pin 3) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2μF or greater.
Input Drive Impedance
As with all high performance, high speed ADCs the
dynamic performance of the LTC2216/LTC2215 can be
inuenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can inuence SFDR. At the falling edge of ENC
the sample and hold circuit will connect the sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2 fENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recommended to have a
source impedance of 100
Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
INPUT DRIVE CIRCUITS
Input Filtering
A rst-order RC low-pass lter at the input of the ADC
can serve two functions: limit the noise from input cir-
cuitry and provide isolation from ADC S/H switching. The
LTC2216/LTC2215 have a very broadband S/H circuit,
DC to 400MHz. This can be used in a wide range of ap-
plications, therefore, it is not possible to provide a single
recommended RC lter.
Figures 3 and 4 show two examples of input RC ltering for
two ranges of input frequencies. In general it is desirable
to make the capacitors as large as can be tolerated–this
will help suppress random noise as well as noise coupled
from the digital circuitry. The LTC2216/LTC2215 do not
require any input lter to achieve data sheet specica-
tions; however, no ltering will put more stringent noise
requirements on the input drive circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2216/LTC2215 being driven by
an RF transformer with a center-tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Figure 3 shows
a 1:1 turns ratio transformer. Other turns ratios can be
used; however, as the turns ratio increases so does the
impedance seen by the ADC. Source impedance greater
than 50
Ω can reduce the input bandwidth and increase
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 100MHz
35Ω
5Ω
35Ω
10Ω
5Ω
0.1μF
AIN
+
AIN
–
8.2pF
2.2μF
8.2pF
VCM
T1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
22165 F03
LTC2216/
LTC2215
APPLICATIONS INFORMATION
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2216CUP#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2216IUP#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2216IUP | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2216CUP | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2215IUP | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2215CUP#PBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 64-QFN |
| LTC2215CUP#TRPBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 64-QFN |
| LTC2215CUP-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Low Noise ADC |
| LTC2215CUP-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Low Noise ADC |
| LTC2215CUP-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Low Noise ADC |
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