参数资料
型号: LTC3728IUH#PBF
厂商: Linear Technology
文件页数: 18/36页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32-QFN
标准包装: 73
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 590kHz
占空比: 99%
电源电压: 3.5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 管件
LTC3728
APPLICATIONS INFORMATION
V OUT ( V IN V OUT )
I L ESR +
themaximumRMScurrentofonechannelmustbeused.
The maximum RMS capacitor current is given by:
1/2
C IN Required I RMS I MAX
V IN
This formula has a maximum at V IN = 2V OUT , where
I RMS = I OUT /2. This simple worst case condition is com-
monly used for design because even signi?cant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled
to meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
The bene?t of the LTC3728 multiphase can be calculated by
using the equation above for the higher power controller
and then calculating the loss that would have resulted if
both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the interleaving of current pulses through
the input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case controller
is adequate for the dual controller design. Remember that
input protection fuse resistance, battery resistance and PC
board trace resistance losses are also reduced due to the
reduced peak currents in a multiphase system. The overall
bene?t of a multiphase design will only be fully realized
when the source impedance of the power supply/battery
is included in the ef?ciency testing. The drains of the
two top MOSFETs should be placed within 1cm of each
other and share a common C IN (s). Separating the drains
and C IN may produce undesirable voltage and current
resonances at V IN .
The selection of C OUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satis?ed the capacitance is adequate for ?ltering.
The output ripple (ΔV OUT ) is determined by:
1
V OUT
8fC OUT
Where f = operating frequency, C OUT = output capacitance,
and ΔI L = ripple current in the inductor. The output ripple is
highest at maximum input voltage since ΔI L increases with
input voltage. With ΔI L = 0.3I OUT(MAX) the output ripple
will typically be less than 50mV at max V IN assuming:
C OUT Recommended ESR < 2 R SENSE
and C OUT > 1/(8fR SENSE )
The ?rst condition relates to the ripple current into the ESR
of the output capacitance while the second term guarantees
that the output capacitance does not signi?cantly discharge
during the operating frequency period due to ripple current.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The I TH pin
OPTI-LOOP compensation components can be optimized
to provide stable, high performance transient response
regardless of the output capacitors selected.
Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Special
polymer surface mount capacitors offer very low ESR but
3728fg
18
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