参数资料
型号: LTC3728IUH#PBF
厂商: Linear Technology
文件页数: 21/36页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32-QFN
标准包装: 73
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 590kHz
占空比: 99%
电源电压: 3.5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 管件
LTC3728
APPLICATIONS INFORMATION
reference by the error ampli?er. The output voltage is given
by the equation:
Soft-Start/Run Function
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
V OUT = 0.8V 1 +
R2
R1
that provide a soft-start function and a means to shut down
the LTC3728. Soft-start reduces the input power source’s
surge currents by gradually increasing the controller’s
where R1 and R2 are de?ned in Figure 2.
SENSE + /SENSE – PINS
The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTV CC . Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTV CC . A differential NPN input
stage is biased with internal resistors from an internal 2.4V
source, as shown in the Functional Diagram. This requires
that current either be sourced or sunk from the SENSE
pins depending on the output voltage. If the output voltage
is below 2.4V, current will ?ow out of both SENSE pins to
current limit (proportional to V ITH ). This pin can also be
used for power supply sequencing.
An internal 1.2μA current source charges up the C SS
capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/
R SENSE to 75mV/R SENSE . The output current limit ramps
up slowly, taking an additional 1.25s/μF to reach full cur-
rent. The output current thus ramps up slowly, reducing
the starting surge current required from the input power
supply. If RUN/SS has been pulled all the way to ground
there is a delay before starting of approximately:
1.2 μ A SS
the main output. The output can be easily preloaded by
the V OUT resistive divider to compensate for the current
t DELAY =
1.5V
C
= ( 1.25s / μ F ) C SS
comparator’s negative input bias current. The maximum
current ?owing out of each pair of SENSE pins is:
I SENSE+ + I SENSE– = (2.4V – V OUT )/24k
t IRAMP =
3V 1.5V
1.2 μ A
C SS = ( 1.25s / μ F ) C SS
Since V OSENSE is servoed to the 0.8V reference voltage,
we can choose R1 in Figure 2 to have a maximum value
to absorb this current.
By pulling both RUN/SS pins below 1V, the LTC3728 is put
into low current shutdown (I Q = 20μA). The RUN/SS pins
can be driven directly from logic, as shown in Figure 7.
R1 (MAX) = 24k
for V OUT < 2.4V
0.8V
2.4V – V OUT
Diode D1 in Figure 7 reduces the start delay but allows
C SS to ramp up slowly providing the soft-start function.
Each RUN/SS pin has an internal 6V Zener clamp (see
the Functional Diagram).
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the V OSENSE
feedback current.
3728fg
21
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