参数资料
型号: LTC3728IUH#PBF
厂商: Linear Technology
文件页数: 26/36页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32-QFN
标准包装: 73
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 590kHz
占空比: 99%
电源电压: 3.5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 管件
LTC3728
APPLICATIONS INFORMATION
R SENSE = 10mΩ and R ESR = 40mΩ (sum of both input
and output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Ef?ciency varies as the inverse square of V OUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become signi?cant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) V IN2 I O(MAX) C RSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% ef?ciency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
losses can be minimized by ensuring C IN has adequate
charge storage and very low ESR at the switching frequency.
A 25W supply will typically require a minimum of 20μF
to 40μF of capacitance having a maximum of 20mΩ to
50mΩ of ESR. The LTC3728 2-phase architecture typically
halves this input capacitance requirement over competing
solutions. Other losses, including Schottky conduction
losses during dead time and inductor core losses, generally
account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V OUT shifts by
an amount equal to ΔI LOAD (ESR), where ESR is the ef-
fective series resistance of C OUT . ΔI LOAD also begins to
charge or discharge C OUT , generating the feedback error
signal that forces the regulator to adapt to the current
change and return V OUT to its steady-state value. During
this recovery time, V OUT can be monitored for excessive
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the I TH pin
not only allows optimization of control loop behavior but
also provides a DC-coupled and AC-?ltered closed loop
response test point. The DC step, rise time and settling
at this test point truly re?ects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The I TH external components shown in the Figure 1
circuit will provide an adequate starting point for most
applications.
The I TH series R C -C C ?lter sets the dominant pole-zero
loop compensation. The values can be modi?ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the ?nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I TH pin waveforms that will
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I TH pin signal, which is
in the feedback loop and is the ?ltered and compensated
control loop response. The gain of the loop will be in-
creased by increasing R C and the bandwidth of the loop
will be increased by decreasing C C . If R C is increased by
the same factor that C C is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
3728fg
26
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