参数资料
型号: LTC3734EUH#TR
厂商: Linear Technology
文件页数: 7/28页
文件大小: 0K
描述: IC CTRLR DC/DC 1PH HI EFF 32QFN
标准包装: 2,500
应用: 控制器,Intel 移动式 CPU
输入电压: 4 V ~ 30 V
输出数: 1
输出电压: 0.7 V ~ 1.71 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 带卷 (TR)
LTC3734
PIN FUNCTIONS
V OA+ , V OA– (Pins 1, 2): Inputs to the Internal Operational
Amplifier.
OAOUT (Pin 3): Output of the Internal Operational
Amplifier.
STP_CPUB (Pin 4): Deep Sleep State Input. When the
signal to this pin is low, the voltage regulator enters deep
sleep state and its output voltage is a certain percentage
lower than the VID commands. This offset percentage is
set by the resistor connected to the RDPSLP pin. When
the signal to this pin is high, the voltage regulator exits
deep sleep state.
SGND (Pin 5): Signal Ground. All small-signal components
and compensation components should connect to this
ground which, in turn, connects to PGND at one point.
SENSE + (Pin 6): The (+) Input to the Differential Current
Comparator. The I TH pin voltage and built-in offsets between
SENSE – and SENSE + pins in conjunction with R SENSE set
the current trip threshold.
SENSE – (Pin 7): The (–) Input to the Differential Current
Comparator.
RDPRSLP (Pin 8): Deeper Sleep State Resistor Pin. Connect
a resistor from this pin to V OA+ . This resistor in conjunc-
tion with the RDPSLP resistor sets the output voltage of
the regulator in deeper sleep state.
RUN/SS (Pin 10): Combination of Soft-Start, Run Control
Input and Short-Circuit Detection Timer. A capacitor to
ground at this pin sets the ramp time to full current output.
Forcing this pin below 1V causes the IC to shut down all
internal circuitry. All functions are disabled in shutdown.
I TH (Pin 11): Error Amplifier Output and Switching
Regulator Compensation Point. The current comparator’s
threshold increases with this control voltage. The normal
voltage range of this pin is from 0V to 2.4V
RBOOT (Pin 12): Boot-Up Resistor Pin. Connect a resistor
from this pin to V OA+ . This resistor sets the output voltage
during the initial boot-up.
VID0–VID5 (Pins 13, 14, 15, 17, 18, 19): VID Control
Logic Input Pins.
NC (Pin 16): Not Connected.
PGND (Pin 20): Driver Power Ground. Connect to sources
of bottom N-channel MOSFETs and the (–) terminals of C IN .
BG (Pin 21): High Current Gate Drive for Bottom N-Channel
MOSFETs. Voltage swing at this pin is from ground to PV CC .
PV CC (Pin 22): Power Supply Pin. The on chip gate drivers
are powered from this voltage source. Decouple to PGND
with a minimum of 4.7μF X5R/X7R ceramic capacitor
placed directly adjacent to the IC.
RDPSLP (Pin 9): Deep Sleep Resistor Pin. Connect a resis-
tor from this pin to V OA+ . This resistor sets the percentage
offset of output voltage in deep sleep state.
3734fa
7
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