参数资料
型号: LTC3831EGN
厂商: Linear Technology
文件页数: 12/20页
文件大小: 0K
描述: IC SW REG CONTROLLR SYNC 16-SSOP
标准包装: 100
应用: 控制器,DDR
输入电压: 3 V ~ 8 V
输出数: 1
输出电压: 1.27 V ~ 4 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP
包装: 管件
产品目录页面: 1336 (CN2011-ZH PDF)
LTC3831
APPLICATIONS INFORMATION
than 7V, a 12V zener diode should be included from PV CC1
to PGND to prevent transients from damaging the circuitry
at PV CC1 or the gate of Q1.
D Z
12V
1N5242
1N5817
1N5817
V IN
1N5817
For applications with a lower V IN supply, a tripling charge
pump circuit shown in Figure 7 can be used to provide
2V IN and 3V IN gate drive for the external top and bottom
MOSFETs respectively. This circuit provides 3V IN – 3V F to
10μF
PV CC2
PV CC1
TG
0.1μF
0.1μF
Q1
L O
V OUT
PV CC1 while Q1 is ON and 2V IN – 2V F to PV CC2 where V F
is the forward voltage of the Schottky diode. The circuit
requires the use of Schottky diodes to minimize forward
LTC3831
BG
Q2
+
C OUT
3831 F07
drop across the diodes at start-up. The tripling charge
pump circuit can rectify any ringing at the drain of Q2 and
provide more than 3V IN at PV CC1 ; a 12V zener diode should
be included from PV CC1 to PGND to prevent transients from
damaging the circuitry at PV CC1 or the gate of Q1.
The charge pump capacitors for PV CC1 refresh when the
BG pin goes high and the switch node is pulled low by
Q2. The BG on time becomes narrow when the LTC3831
operates at maximum duty cycle (95% typical) which
can occur if the input supply rises more slowly than the
soft-start capacitor or the input voltage droops during
load transients. If the BG on time gets so narrow that the
switch node fails to pull completely to ground, the charge
pump voltage may collapse or fail to start causing excessive
dissipation in external MOSFET Q1. This is most likely with
low V CC voltages and high switching frequencies, coupled
with large external MOSFETs that slow the BG and switch
node slew rates.
The LTC3831 overcomes this problem by sensing the
PV CC1 voltage when TG is high. If PV CC1 is less than 2.5V
above V CC , the maximum TG duty cycle is reduced to
70% by clamping the COMP pin at 1.8V (Q C in the Block
Diagram). This increases the BG on time and allows the
charge pump capacitors to be refreshed.
Figure 7. Tripling Charge Pump
Connecting the Ratiometric Reference Input
The LTC3831 derives its ratiometric reference, V REF ,
using an internal resistor divider. The top and bottom of
the resistor divider is connected to the R + and R – pins
respectively. This permits the output voltage to track at
a ratio of the differential voltage at R + and R – .
The LTC3831 can operate with a minimum V FB of 1.1V
and maximum V FB of (V CC – 1.75V). With R – connected
to GND, this gives a V R+ input range of 2.2V to (2 ? V CC
– 3.5V). If V R+ is higher than the permitted input voltage,
increase the V CC voltage to raise the input range.
In a typical DDR memory termination application as shown
in Figure 1, R + is connected to V DDQ , the supply voltage
of the interface, and R – to GND. The output voltage V TT is
connected to the FB pin, so V TT = 0.5 ? V DDQ .
If a ratio greater than 0.5 is desired, it can be achieved
using an external resistor divider connected to V TT and
FB pin. Figure 8 shows an application that generates a
V TT of 0.6 ? V DDQ .
For applications using an external supply to power PV CC1 ,
this supply must also be higher than V CC by at least 2.5V
to ensure normal operation.
3831fb
12
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