参数资料
型号: LTC3831EGN
厂商: Linear Technology
文件页数: 7/20页
文件大小: 0K
描述: IC SW REG CONTROLLR SYNC 16-SSOP
标准包装: 100
应用: 控制器,DDR
输入电压: 3 V ~ 8 V
输出数: 1
输出电压: 1.27 V ~ 4 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP
包装: 管件
产品目录页面: 1336 (CN2011-ZH PDF)
LTC3831
PIN FUNCTIONS
FREQSET (Pin 11): Frequency Set. Use this pin to adjust
the free-running frequency of the internal oscillator. With
the pin ?oating, the oscillator runs at about 200kHz. A
resistor from FREQSET to ground speeds up the oscillator;
a resistor to V CC slows it down.
I MAX (Pin 12): Current Limit Threshold Set. I MAX sets the
threshold for the internal current limit comparator. If I FB
drops below I MAX with TG on, the LTC3831 goes into cur-
rent limit. I MAX has an internal 12μA pull-down to GND.
Connect this pin to the main V IN supply at the drain of
Q1, through an external resistor to set the current limit
threshold. Connect a 0.1μF decoupling capacitor across
this resistor to ?lter switching noise.
I FB (Pin 13): Current Limit Sense. Connect this pin to the
switching node at the source of Q1 and the drain of Q2
BLOCK DIAGRAM
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging I FB .This pin is used
for sensing the voltage drop across the upper N-channel
MOSFET, Q1.
V CC (Pin 14): Power Supply Input. All low power internal
circuits draw their supply from this pin. This pin requires
a 4.7μF bypass capacitor to GND.
PV CC2 (Pin 15): Power Supply Input for BG. Connect this
pin to the main high power supply.
BG (Pin 16): Bottom Driver Output . Connect this pin to
the gate of the lower N-channel MOSFET, Q2. This output
swings from PGND to PV CC2 . It remains low when TG is high
or during shutdown mode. To prevent output undershoot
during a soft-start cycle, BG is held low until TG ?rst goes
high (FFBG in the Block Diagram).
SHDN
100μs DELAY
LOGIC AND
THERMAL SHUTDOWN
DISABLE GATE DRIVE
V CC
INTERNAL
POWER DOWN
OSCILLATOR
PV CC1
FREQSET
S
Q
TG
PWM
COMP
R
Q
PV CC2
BG
12μA
FFBG
SS
QSS
S
Q
ENABLE
BG
PGND
POR
R
FB
R +
+
ERR
MIN
+
MAX
+
V REF + 3%
24k
750Ω
V REF
V REF – 3%
V REF + 3%
V REF
750Ω
CC
I FB
V REF – 3%
Q C
2.2V
1.2V
DISABLE
I LIM
+
12μA
I MAX
+
PV CC1
24k
3830 BD
R –
GND
V
V CC1 + 2.5V
3831fb
7
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