参数资料
型号: LTC3831EGN
厂商: Linear Technology
文件页数: 6/20页
文件大小: 0K
描述: IC SW REG CONTROLLR SYNC 16-SSOP
标准包装: 100
应用: 控制器,DDR
输入电压: 3 V ~ 8 V
输出数: 1
输出电压: 1.27 V ~ 4 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP
包装: 管件
产品目录页面: 1336 (CN2011-ZH PDF)
LTC3831
TYPICAL PERFORMANCE CHARACTERISTICS
PV CC Supply Current
vs Gate Capacitance
TG Rise/Fall Time
vs Gate Capacitance
Transient Response
50
40
T A = 25°C
PV CC1,2 = 12V
200
180
160
140
T A = 25°    C
V OUT
50mV/
30
20
PV CC1,2 = 5V
120
100
80
60
t f AT PV CC1,2 = 5V
t r AT PV CC1,2 = 5V
DIV
I LOAD
2A/DIV
10
0
0
1 2 3
4 5
6 7
8
9
10
40
20
0
0
1
2
3
4
t f AT PV CC1,2 = 12V
t r AT PV CC1,2 = 12V
5 6 7 8 9
10
50μs/DIV
3831 G22
GATE CAPACITANCE AT TG AND BG (nF)
3831 G20
PIN FUNCTIONS
GATE CAPACITANCE AT TG AND BG (nF)
3831 G21
TG ( Pin 1): Top Driver Output. Connect this pin to the
gate of the upper N-channel MOSFET, Q1. This output
swings from PGND to PV CC1 . It remains low if BG is high
or during shutdown mode.
PV CC1 (Pin 2): Power Supply Input for TG. Connect this pin
to a potential of at least V IN + V GS(ON)(Q1) . This potential
can be generated using an external supply or a simple
charge pump connected to the switching node between
the upper MOSFET and the lower MOSFET.
PGND (Pin 3): Power Ground. Both drivers return to
this pin. Connect this pin to a low impedance ground in
close proximity to the source of Q2. Refer to the Layout
Consideration section for more details on PCB layout
techniques.
GND (Pin 4): Signal Ground. All low power internal cir-
cuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at
the LTC3831.
R – , R + (Pins 5, 7): These two pins connect to the internal
resistor divider that generate the internal ratiometric refer-
ence for the error ampli?er. The reference voltage is set
at 0.5 ? (V R + – V R –).
resistor divider. The FB pin is servoed to the ratiometric
reference under closed-loop conditions. The LTC3831 can
operate with a minimum V FB of 1.1V and maximum V FB
of (V CC – 1.75V).
SHDN (Pin 8): Shutdown. A TTL compatible low level at
SHDN for longer than 100μs puts the LTC3831 into shut-
down mode. In shutdown, TG and BG go low, all internal
circuits are disabled and the quiescent current drops to
10μA max. A TTL compatible high level at SHDN allows
the part to operate normally. This pin also double as an
external clock input to synchronize the internal oscillator
with an external clock.
SS (Pin 9): Soft-Start. Connect this pin to an external
capacitor, C SS , to implement a soft-start function. If the
LTC3831 goes into current limit, C SS is discharged to
reduce the duty cycle. C SS must be selected such that
during power-up, the current through Q1 will not exceed
the current limit level.
COMP (Pin 10): External Compensation. This pin internally
connects to the output of the error ampli?er and input of
the PWM comparator. Use a RC + C network at this pin
to compensate the feedback loop to provide optimum
transient response.
FB (Pin 6): Feedback Voltage. FB senses the regulated
output voltage either directly or through an external
3831fb
6
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