参数资料
型号: LTC4259CGW#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO36
封装: 0.300 INCH, PLASTIC, SSOP-36
文件页数: 27/32页
文件大小: 324K
代理商: LTC4259CGW#PBF
LTC4259
4
4259i
Note 6: Voltage at the Ethernet connector must be at least – 44V for
IEEE 802.3af compliance. The minimum VEE supply voltage must take
account for the drop across the diode DAC in Figure 15.
Note 7: Unless otherwise specified, AC disconnect specifications require
the following conditions: the DETECT
n pin is connected to the port as
shown in Figure 1, a valid sine wave is applied to OSCIN, the OSCFAIL bit
is cleared and AC disconnect is enabled.
Note 8: Guaranteed by design, not subject to test.
Note 9: Values measured at VILD and VIHD.
Note 10: If fault occurs during an I2C transaction, INT pin will not be pulled
down until a stop condition is present on the I2C bus.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: DGND to AGND voltages beyond
±100mV will prevent proper
operation of the classification function.
Note 3: An internal clamp limits the GATE pins to a minimum of 12V above
VEE. Driving this pin beyond the clamp may damage the part.
Note 4: When a port powers on or off, the transient voltage on the port
couples through CDET (Figure 15). The LTC4259 contains internal
protection circuitry to withstand transient currents of up to 80mA for 5ms.
As long as the absolute value of the current remains below 80mA, the
LTC4259 will keep the voltage at the DETECT
n pin within the absolute
maximum voltage range. A properly sized RDET will limit the current to less
than 60mA.
Note 5: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground (AGND and DGND)
unless otherwise specified.
ELECTRICAL CHARACTERISTICS The q denotes the specificatiions which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V, VEE = –48V unless otherwise noted (Note 5).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DCCLMAX
Maximum Current Limit Duty Cycle
q
5.8
6.3
6.7
%
tDIS
Disconnect Delay
tDIS1 = 0, tDIS0 = 0 (Figures 4, 5)
q
300
360
400
ms
tDIS1 = 0, tDIS0 = 1
q
75
90
100
ms
tDIS1 = 1, tDIS0 = 0
q
150
180
200
ms
tDIS1 = 1, tDIS0 = 1
q
600
720
800
ms
tVMIN
DC Disconnect Minimum Pulse
VSENSEn – VEE > 5mV, VOUTn = –48V (Figure 4)
q
0.02
1
ms
Width Sensitivity
I2C Timing
fSCLK
Clock Frequency
(Note 8)
q
400
kHz
t1
Bus Free Time
Figure 6 (Notes 8, 9)
q
1.3
s
t2
Start Hold Time
Figure 6 (Notes 8, 9)
q
600
ns
t3
SCL Low Time
Figure 6 (Notes 8, 9)
q
1.3
s
t4
SCL High Time
Figure 6 (Notes 8, 9)
q
600
ns
t5
Data Hold Time
Figure 6 (Notes 8, 9)
q
150
ns
t6
Data Set-Up Time
Figure 6 (Notes 8, 9)
q
200
ns
t7
Start Set-Up Time
Figure 6 (Notes 8, 9)
q
600
ns
t8
Stop Set-Up Time
Figure 6 (Notes 8, 9)
q
600
ns
tr
SCL, SDAIN Rise Time
Figure 6 (Notes 8, 9)
q
20
300
ns
tf
SCL, SDAIN Fall Time
Figure 6 (Notes 8, 9)
q
20
150
ns
tFLTINT
Fault Present to INT Pin Low
(Notes 8, 9, 10)
q
20
150
ns
tSTOPINT
Stop Condition to INT Pin Low
(Notes 8, 9, 10)
q
60
200
ns
tARAINT
ARA to INT Pin High Time
(Notes 8, 9)
q
20
300
ns
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