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参数资料
| 型号： | LTC6945IUFD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER INTEGER N 28QFN |
| 软件下载： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 标准包装： | 73 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 6GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.15 V ~ 5.25 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（4x5） |
| 包装： | 管件 |
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LTC6945
18
6945f
APPLICATIONS INFORMATION
INTRODUCTION
A PLL is a complex feedback system that may conceptually
be considered a frequency multiplier. The system multiplies
the frequency input at REF± and outputs a higher frequency
at RF±. The PFD, charge pump, N divider, and external VCO
and loop filter form a feedback loop to accurately control
the output frequency (see Figure 15). The R and O dividers
are used to set the output frequency resolution.
Using the above equations, the output frequency resolution
fSTEP produced by a unit change in N is given by Equation 5:
f
STEP =
f
REF
R O
(5)
LOOP FILTER DESIGN
A stable PLL system requires care in selecting the external
loop filter values. The Linear Technology PLLWizard ap-
plication, available from www.linear.com, aids in design
and simulation of the complete system.
The loop design should use the following algorithm:
1. Determine the output frequency, fRF, and frequency
step size, fSTEP, based on application constraints. Using
Equations 2, 3, 4 and 5, change fREF, N, R and O until
the application frequency constraints are met. Use the
minimum R value that still satisfies the constraints.
2. Select the loop bandwidth BW constrained by fPFD. A
stable loop requires that BW is less than fPFD by at least
a factor of 10.
3. Select loop filter component RZ and charge pump cur-
rent ICP based on BW and the VCO gain factor KVCO.
BW (in Hz) is approximated by the following equation:
BW
I
CP RZ K VCO
2
π N
or :
R
Z =
2
π BW N
I
CP K VCO
(6)
where KVCO is in Hz/V, ICP is in Amps, and RZ is in Ohms.
KVCO is the VCO’s frequency tuning sensitivity, and
may be determined from the VCO specifications. Use
ICP = 11.2mA to lower in-band noise unless component
values force a lower setting.
Figure 15. PLL Loop Diagram
R_DIV
N_DIV
÷R
÷N
÷O
fPFD
LTC6945
REF±
(fREF)
(fVCO)
KPFD
KVCO
RF±
(fRF)
CP
RZ
CI
CP
LOOP FILTER
LF(s)
6945 F15
VCO±
ICP
O_DIV
OUTPUT FREQUENCY
When the loop is locked, the frequency fVCO (in Hz)
produced at the output of the VCO is determined by the
reference frequency fREF, and the R and N divider values,
given by Equation 2:
f
VCO =
f
REF N
R
(2)
Here, the PFD frequency fPFD produced is given by the
following equation:
f
PFD =
f
REF
R
(3)
and fVCO may be alternatively expressed as:
fVCO = fPFD N
The output frequency fRF produced at the output of the O
divider is given by Equation 4:
f
RF =
f
VCO
O
(4)
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| LTC6946IUFD-1#PBF | 功能描述:IC INTEGER-N PLL W/VCO 28-QFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| LTC6946IUFD-1#TRPBF | 功能描述:IC INTEGER-N PLL W/VCO 28QFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
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