- 您现在的位置：买卖IC网 > PDF目录9090 > LTC6945IUFD#PBF (Linear Technology)IC SYNTHESIZER INTEGER N 28QFN PDF资料下载
参数资料
| 型号： | LTC6945IUFD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 4/28页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER INTEGER N 28QFN |
| 软件下载： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 标准包装： | 73 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 6GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.15 V ~ 5.25 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（4x5） |
| 包装： | 管件 |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
LTC6945
12
6945f
OPERATION
Figure 5. Simplified Charge Pump Schematic
CHARGE PUMP
The charge pump, controlled by the PFD, forces sink
(DOWN) or source (UP) current pulses onto the CP pin,
which should be connected to an appropriate loop filter.
See Figure 5 for a simplified schematic of the charge pump.
inverting op amps in conjunction with positive-slope tuning
oscillators. A passive loop filter as shown in Figure 15,
used in conjunction with a positive-slope VCO, requires
CPINV = 0.
CHARGE PUMP FUNCTIONS
The charge pump contains additional features to aid
in system start-up and monitoring. See Table 6 for a
summary.
Table 6. CP Function Bit Descriptions
BIT
DESCRIPTION
CPCHI
Enable High Voltage Output Clamp
CPCLO
Enable Low Voltage Output Clamp
CPDN
Force Sink Current
CPINV
Invert PFD Phase
CPMID
Enable Mid-Voltage Bias
CPRST
Reset PFD
CPUP
Force Source Current
CPWIDE
Extend Current Pulse Width
THI
High Voltage Clamp Flag
TLO
Low Voltage Clamp Flag
The CPCHI and CPCLO bits found in register h0A enable
the high and low voltage clamps, respectively. When CPCHI
is enabled and the CP pin voltage exceeds approximately
VCP+ – 0.9V, the THI status flag is set, and the charge pump
sourcing current is disabled. Alternately, when CPCLO is
enabled and the CP pin voltage is less than approximately
0.9V, the TLO status flag is set, and the charge pump sinking
current is disabled. See Figure 5 for a simplified schematic.
The CPMID bit also found in register h0A enables a
resistive VCP+/2 output bias which may be used to pre-
bias troublesome loop filters into a valid voltage range
before attempting to lock the loop. When using CPMID,
it is recommended to also assert the CPRST bit, forcing
a PFD reset. Both CPMID and CPRST must be set to “0”
for normal operation.
The CPUP and CPDN bits force a constant ICP source or
sink current, respectively, on the CP pin. The CPRST bit
may also be used in conjunction with the CPUP and CPDN
bits, allowing a pre-charge of the loop to a known state,
if required. CPUP, CPDN, and CPRST must be set to “0”
to allow the loop to lock.
25
+
–
+
–
CP
THI
0.9V
VCP
+
VCP
+
TLO
+
–
0.9V
6945 F05
+
–
VCP
+/2
CPMID
CPUP
UP
CPDN
DOWN
The output current magnitude ICPmaybesetfrom250μAto
11.2mA using the CP[3:0] bits found in serial port register
h09. A larger ICP can result in lower in-band noise due to
the lower impedance of the loop filter components. See
Table 5 for programming specifics and the Applications
Information section for loop filter examples.
Table 5. CP[3:0] Programming
CP[3:0]
ICP
0
250μA
1
350μA
2
500μA
3
700μA
4
1.0mA
5
1.4mA
6
2.0mA
7
2.8mA
8
4.0mA
9
5.6mA
10
8.0mA
11
11.2mA
12 to 15
Invalid
The CPINV bit found in register h0A should be set for ap-
plications requiring signal inversion from the PFD, such
as for loops using negative-slope tuning oscillators, or
相关PDF资料 |
PDF描述 |
|---|---|
| X9409WV24T1 | IC XDCP QUAD 64-TAP 10K 24-TSSOP |
| V150A3V3H200B | CONVERTER MOD DC/DC 3.3V 200W |
| X9410YS24I-2.7 | IC XDCP DUAL 64-TAP 2.5K 24-SOIC |
| X9410YS24I | IC XDCP DUAL 64-TAP 2.5K 24-SOIC |
| X9410YS24-2.7 | IC XDCP DUAL 64-TAP 2.5K 24-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC6946-1 | 制造商:LINER 制造商全称:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-2 | 制造商:LINER 制造商全称:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-3 | 制造商:LINER 制造商全称:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946IUFD-1#PBF | 功能描述:IC INTEGER-N PLL W/VCO 28-QFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| LTC6946IUFD-1#TRPBF | 功能描述:IC INTEGER-N PLL W/VCO 28QFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
发布紧急采购，3分钟左右您将得到回复。