LXT384
—
Octal T1/E1/J1 Transceiver
42
Datasheet
Table 18. Software Reset Register, RES (0Ah)
Bit
Name
Function
7-0
RES7-RES0
Writing to this register initiates a 1 microsecond reset cycle, except in Intel non-
multiplexed mode. This operation sets all LXT384 registers to their default values.
When using Intel non-multiplexed host mode, extend cycle time to 2 microseconds.
Please refer to Host Mode section for details.
Table 19. Performance Monitoring Register, MON (0Bh)
Bit
Name
Function
3-0
A3:A0
Protected Monitoring selection. See
Table 1
,
page 15
.
4-7
reserved
Reserved.
Table 20. Digital Loopback Register, DL (0Ch)
Bit
1
Name
Function
2
7-0
DL7-DL0
Setting a bit to
“
1
”
enables digital loopback for the respective transceiver.
1. On power up all register bits are set to
“
0
”
.
2. During digital loopback LOS and TAOS stay active and independent of TCLK, while data received on
TPOS/TNEG/CKLK is looped back to RPOS/RNEG/RCLK.
Table 21. LOS/AIS Criteria Register, LCS (0Dh)
Bit
1
Name
Function
2
7-0
LCS7-LCS0
T1 Mode
Don
’
t care. T1.231 compliant LOS/AIS detection is used.
E1 Mode
Setting a bit to
“
1
”
selects the ETSI 300233 LOS. Setting a bit to
“
0
”
selects G.775
LOS mode. AIS works correctly for both ETSI and ITU when the bit is cleared to
“
0
”
.
See errata 10.3 or higher for a way to implement ETSI LOS and AIS.
1. On power-on reset the register is set to
“
0
”
.
2. T1 or E1 operation mode is determined by the PSDAT settings.
Table 22. Automatic TAOS Select Register, ATS (0Eh)
Bit
1
Name
Function
7-0
ATS7-ATS0
Setting a bit to
“
1
”
enables automatic TAOS generation whenever a LOS condition is
detected in the respective transceiver.
1. On power-on reset the register is set to
“
0
”
.
2. This feature is not available in data recovery and line driver mode (MCLK= High and TCLK = High).