参数资料
型号: LXT384BE
元件分类: 通信、网络模块及开发工具
英文描述: Telecomm/Datacomm
中文描述: 电信/数据通信
文件页数: 62/80页
文件大小: 1112K
代理商: LXT384BE
LXT384
Octal T1/E1/J1 Transceiver
62
Datasheet
RCLK Rising to RPOS/RNEG hold time
E1
Thr
200
244
ns
T1
200
324
ns
Delay time between RPOS/RNEG and RCLK
5
ns
MCLK = H
3
Figure 19. Receive Clock Timing Diagram
Table 46. JTAG Timing Characteristics
Parameter
Sym
Min.
Typ
Max
Unit
Test Conditions
Cycle time
Tcyc
200
-
-
ns
J-TMS/J-TDI to J-TCK rising edge time
Tsut
50
-
-
ns
J-CLK rising to J-TMS/L-TDI hold time
Tht
50
-
-
ns
J-TCLK falling to J-TDO valid
Tdod
-
-
50
ns
Table 45. Receive Timing Characteristics (Sheet 2 of 2)
Parameter
Sym
Min.
Typ
Max
Unit
Test Condition
1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and
minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823).
2. Clock recovery is disabled in this mode.
3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit.
4. For all digital outputs.
CLKE = 0
RPOS
RNEG
CLKE = 1
RPOS
RNEG
RCLK
tPW
tPWH
tSUR
tPWL
tHR
tHR
tSUR
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