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参数资料
型号： M1A3PE1500-FGG676I
厂商： Microsemi SoC
文件页数： 59/162页
文件大小： 0K
描述： IC FPGA 1KB FLASH 1.5M 676-FBGA
标准包装： 40
系列： ProASIC3E
RAM 位总计： 276480
输入/输出数： 444
门数： 1500000
电源电压： 1.425 V ~ 1.575 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 676-BGA
供应商设备封装： 676-FBGA（27x27）
Revision 13
5-1
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the ProASIC3E datasheet.
Revision
Changes
Page
Revision 13
(January 2013)
In the "Features and Benefits" section, updated the Clock Conditioning Circuit
(CCC) and PLL Wide Input Frequency Range from ’1.5 MHz to 200 MHz’ to
’1.5MHz to 350 MHz’ based on Table 2-98 ProASIC3E CCC/PLL Specification
(SAR 22196).
1-I
The "ProASIC3E Ordering Information" section has been updated to mention "Y"
as "Blank" mentioning "Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43220).
1-III
Added a note to Table 2-2 Recommended Operating Conditions 1 (SAR 42716):
The programming temperature range supported is Tambient = 0°C to 85°C.
2-2
The note in Table 2-98 ProASIC3E CCC/PLL Specification referring the reader
to SmartGen was revised to refer instead to the online help associated with the
core (SAR 42571).
2-69
Libero Integrated Design Environment (IDE) was changed to Libero System-on-
Chip (SoC) throughout the document (SAR 40285).
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
NA
Revision 12
(September 2012)
The "Security" section was modified to clarify that Microsemi does not support
read-back of programmed data.
1-1
Revision 11
(August 2012)
Added a Note stating "VMV pins must be connected to the corresponding VCCI pins.
See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further
information.
" to Table 2-1 Absolute Maximum Ratings and Table 2-2
Recommended Operating Conditions 1 (SAR 38322).
2-1
2-2
The drive strength, IOL, and IOH value for 3.3 V GTL and 2.5 V GTL was
changed from 25 mA to 20 mA in the following tables (SAR 31924):
Table 2-13 Summary of Maximum and Minimum DC Input and Output Levels
Table 2-17 Summary of I/O Timing Characteristics—Software Default Settings
Table 2-19 I/O Output Buffer Maximum Resistances1
Table 2-48 Minimum and Maximum DC Input and Output Levels (3.3 V GTL)
Table 2-51 Minimum and Maximum DC Input and Output Levels (2.5 V GTL)
Also added note stating "Output drive strength is below JEDEC specification." for
Tables 2-17 and 2-19.
Additionally, the IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were
corrected from 51 to 35 (for 3.3 V GTL+) and from 40 to 33 (for 2.5 V GTL+) in
table Table 2-13 (SAR 39714).
2-16
2-19
2-20
2-38
2-39
Table 2-22 Duration of Short Circuit Event Before Failure was revised to change
the maximum temperature from 110°C to 100°C, with an example of six months
instead of three months (SAR 37934).
2-22
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR
34796):
"It uses a 5 V–tolerant input buffer and push-pull output buffer." This change was
made in revision 10 and omitted from the change table in error.
2-29
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