收藏本站
参数资料
型号： M1A3PE1500-FGG676I
厂商： Microsemi SoC
文件页数： 80/162页
文件大小： 0K
描述： IC FPGA 1KB FLASH 1.5M 676-FBGA
标准包装： 40
系列： ProASIC3E
RAM 位总计： 276480
输入/输出数： 444
门数： 1500000
电源电压： 1.425 V ~ 1.575 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 676-BGA
供应商设备封装： 676-FBGA（27x27）
ProASIC3E DC and Switching Characteristics
2-10
Revision 13
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on
page 2-11
.
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on
page 2-11
.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.
1 is the I/O buffer enable rate—guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations—guidelines are provided in Table 2-12 on
page 2-11
.
FWRITE-CLOCK is the memory write clock frequency.
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-12 on
page 2-11
.
PLL Contribution—PPLL
PPLL = PAC13 + PAC14 * FCLKOUT
FCLKOUT is the output clock frequency.1
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
相关PDF资料
PDF描述
93LC76B-I/SN IC EEPROM 8KBIT 2MHZ 8SOIC
EP2S15F484C4 IC STRATIX II FPGA 15K 484-FBGA
24AA32A-I/P IC EEPROM 32KBIT 400KHZ 8DIP
EPF10K40RC208-3 IC FLEX 10K FPGA 40K 208-RQFP
AFS1500-1FG484 IC FPGA 8MB FLASH 1.5M 484-FBGA
相关代理商/技术参数
参数描述
M1A3PE1500-FGG896 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
M1A3PE1500-FGG896ES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
M1A3PE1500-FGG896I 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
M1A3PE1500-FGG896PP 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
M1A3PE1500-FPQ208 制造商:Microsemi Corporation 功能描述:FPGA PROASIC3E 1.5M GATES 193MHZ 130NM 1.5V 208PQFP - Trays
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*