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参数资料
| 型号： | M1A3PE1500-FGG676I |
| 厂商： | Microsemi SoC |
| 文件页数： | 64/162页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1KB FLASH 1.5M 676-FBGA |
| 标准包装： | 40 |
| 系列： | ProASIC3E |
| RAM 位总计： | 276480 |
| 输入/输出数： | 444 |
| 门数： | 1500000 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 676-BGA |
| 供应商设备封装： | 676-FBGA（27x27） |
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Datasheet Information
5-6
Revision 13
v2.1
(continued)
The words "ambient temperature" were added to the temperature range in the
"Temperature Grade Offerings", "Speed Grade and Temperature Grade Matrix",
and "Speed Grade and Temperature Grade Matrix" sections.
iii, iv, iv
The "Clock Conditioning Circuit (CCC) and PLL" section was updated.
i
The caption "Main (chip)" in Figure 2-9 Overview of Automotive ProASIC3
VersaNet Global Network was changed to "Chip (main)."
2-9
The TJ parameter in Table 3-2 Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 4–6 were added.
3-2
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
2-15
v2.0
(April 2007)
In the "Temperature Grade Offerings" section, Ambient was deleted.
iii
Ambient was deleted from "Temperature Grade Offerings".
iii
Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".
iv
The "PLL Macro" section was updated to include power-up information.
2-15
Table 2-13 ProASIC3E CCC/PLL Specification was updated.
2-30
Figure 2-19 Peak-to-Peak Jitter Definition is new.
2-18
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
2-21
The "RESET" section was updated with read and write information.
2-25
The "RESET" section was updated with read and write information.
2-25
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
2-28
In the Table 2-15 Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
2-34
Table 2-45 I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E
Devices was updated.
2-64
Notes 3, 4, and 5 were added to Table 2-17 Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
2-40
The "VCCPLF PLL Supply Voltage" section was updated.
2-50
The "VPUMP Programming Supply Voltage" section was updated.
2-50
The "GL Globals" section was updated to include information about direct input
into quadrant clocks.
2-51
VJTAG was deleted from the "TCK Test Clock" section.
2-51
In Table 2-22 Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
2-51
Ambient was deleted from Table 3-2 Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
3-2
Note 3 is new in Table 3-4 Overshoot and Undershoot Limits (as measured on
quiet I/Os).
3-2
In EQ 3-2, 150 was changed to 110 and the result changed to 5.88.
3-5
Revision
Changes
Page
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