参数资料
型号: M29W800B
厂商: 意法半导体
英文描述: 8Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Single Supply Flash Memory(8Mb低压闪速存储器)
中文描述: 8Mbit(1兆x8或512KB的x16插槽,引导块)低电压单电源闪存(8兆低压闪速存储器)
文件页数: 20/33页
文件大小: 229K
代理商: M29W800B
Symbol
Alt
Parameter
M29W800T / M29W800B
Unit
-120
-150
V
CC
= 2.7V to 3.6V
C
L
= 100pF
V
CC
= 2.7V to 3.6V
C
L
= 100pF
Min
Max
Min
Max
t
AVAV
t
WC
Address Validto Next Address Valid
120
150
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
0
0
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
50
65
ns
t
DVWH
t
DS
Input Valid to Write Enable High
50
65
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
0
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
30
35
ns
t
AVWL
t
AS
Address Valid to Write Enable Low
0
0
ns
t
WLAX
t
AH
Write Enable Low to Address Transition
50
65
ns
t
GHWL
Output Enable High to Write Enable Low
0
0
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
μ
s
t
WHGL
t
OEH
Write Enable High to Output Enable Low
0
0
ns
t
PHPHH
(1,2)
t
VIDR
RP Rise Timeto V
ID
500
500
ns
t
PLPX
t
RP
RP Pulse Width
500
500
ns
t
WHRL
(1)
t
BUSY
Program Erase Valid to RB Delay
90
90
ns
t
PHWL(1)
t
RSP
RP High to Write Enable Low
4
4
μ
s
Notes:
1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotectionoperation.
Table15B. Write AC Characteristics,Write Enable Controlled
(T
A
= 0 to 70
°
C, –20 to 85
°
C or–40 to 85
°
C)
Block Erase (BE) Instruction
. This instruction
uses a minimum of six write cycles. The Erase
Set-upcommand80h is written to addressAAAAh
in the Byte-wideconfigurationor address5555h in
theWord-wideconfigurationon thirdcycleafter the
two Coded cycles. The Block Erase Confirm com-
mand30his similarlywrittenonthesixthcycleafter
anothertwo Coded cycles. During the inputof the
secondcommandan addresswithintheblockto be
erasedis given andlatchedintothememory.Addi-
tional block Erase Confirm commands and block
addresses can be written subsequently to erase
other blocks in parallel, without further Coded cy-
cles. The erase will start after the erase timeout
period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for
other blocks must be given within this delay. The
inputof a newEraseConfirm commandwill restart
the timeout period. The status of the internaltimer
canbe monitoredthrough the levelof DQ3,if DQ3
is ’0’ the Block Erase Command has been given
andthe timeoutis running,ifDQ3is ’1’,thetimeout
hasexpiredand theP/E.C.is erasingtheBlock(s).
If the second command given is not an erase
confirm or if the Coded cycles are wrong, the
instruction aborts, and the device is reset to Read
Array. It is notnecessarytoprogramthe blockwith
00h as the P/E.C. will do this automaticallybefore
to erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register
statusbits.
20/33
M29W800T, M29W800B
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