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参数资料
| 型号： | M306K9F8LRP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 16 X 16 MM, 0.40 MM PITCH, PLASTIC, TQFP-144 |
| 文件页数： | 70/101页 |
| 文件大小： | 2590K |
| 代理商： | M306K9F8LRP |
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Interrupt
Rev.1.00
Jun 06, 2003
page 53 of 290
M16C/6K9 Group
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC)
are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Fig.DD-7 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM
instruction alone can save all the registers except the stack pointer (SP).
Fig.DD-7 State of stack before and after acceptance of interrupt request
Address
Content of previous stack
Stack area
[SP]
Stack pointer
value before
interrupt occurs
m
m – 1
m – 2
m – 3
m – 4
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB
LSB
m
m – 1
m – 2
m – 3
m – 4
Address
Flag register (FLGL)
Content of previous stack
Stack area
Flag register
(FLGH)
Program
counter (PCH)
[SP]
New stack
pointer value
Content of previous stack
m + 1
MSB
LSB
Program counter (PCL)
Program counter (PCM)
The operation of saving registers carried out in the interrupt sequence is dependent on whether the content
of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the
stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter
(PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Fig.DD-8
shows the operation of the saving registers.
Note: Stack pointer is indicated by U flag when software number 32 - 63 INT command is executed,
otherwise is indicated by ISP.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
(1) Saved simultaneously,
all 16 bits
(2) Stack pointer (SP) contains odd number
[SP]
(Odd)
[SP] – 1 (Even)
[SP] – 2 (Odd)
[SP] – 3 (Even)
[SP] – 4 (Odd)
[SP] – 5 (Even)
Address
Sequence in which order
registers are saved
(2)
(1)
Finished saving registers
in four operations.
(3)
(4)
(1) Stack pointer (SP) contains even number
[SP]
(Even)
[SP] – 1 (Odd)
[SP] – 2 (Even)
[SP] – 3 (Odd)
[SP] – 4 (Even)
[SP] – 5 (Odd)
Address
Program counter (PCM)
Stack area
Flag register (FLGL)
Program counter (PCL)
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
Program counter (PCM)
Stack area
Flag register (FLGL)
Program counter (PCL)
Saved
simultaneously,
all 8 bits
Flag register
(FLGH)
Flag register
(FLGH)
Program
counter (PCH)
Program
counter (PCH)
Fig.DD-8 Operation of saving registers
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