参数资料
型号: M34501M2-XXXFP
元件分类: 微控制器/微处理器
英文描述: 4-BIT, MROM, MICROCONTROLLER, PDSO20
封装: 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件页数: 39/118页
文件大小: 952K
代理商: M34501M2-XXXFP
4501 Group
Rev.3.01
2005.02.07
page 25 of 112
REJ03B0104-0301
TIMERS
The 4501 Group has the following timers.
Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a set-
ting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload reg-
ister, and count continues (auto-reload function).
Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency divid-
ing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
Fig. 21 Auto-reload function
Count source
Instruction clock
Prescaler output (ORCLK)
Timer 1 underflow
Prescaler output (ORCLK)
CNTR input
System clock
Instruction clock
Structure
Frequency divider
8-bit programmable
binary down counter
(link to INT input)
8-bit programmable
binary down counter
16-bit fixed dividing
frequency binary down
counter
Circuit
Prescaler
Timer 1
Timer 2
16-bit timer
Use of output signal
Timer 1 and 2 count sources
Timer 2 count source
CNTR output
Timer 1 interrupt
CNTR output
Timer 2 interrupt
Watchdog timer
(The 16th bit is counted twice)
Frequency
dividing ratio
4, 16
1 to 256
65536
Control
register
W1
W2
W6
W2
W6
The 4501 Group timer consists of the following circuits.
Prescaler : frequency divider
Timer 1 : 8-bit programmable timer
Timer 2 : 8-bit programmable timer
(Timers 1 and 2 have the interrupt function, respectively)
16-bit timer
Prescaler and timers 1 and 2 can be controlled with the timer con-
trol registers W1, W2 and W6. The 16-bit timer is a free counter
which is not controlled with the control register.
Each function is described below.
Table 9 Function related timers
FF16
n
0016
n : Counter initial value
Count starts
Reload
1st underflow
2nd underflow
n+1 count
Time
An interrupt occurs or
a skip instruction is executed.
Timer interrupt
request flag
T
h
e
c
o
n
te
n
ts
o
f
c
o
u
n
te
r
“1”
“0”
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