- 您现在的位置：买卖IC网 > PDF目录67761 > M34518E8SP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP32 PDF资料下载
参数资料
| 型号： | M34518E8SP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDIP32 |
| 封装： | 8.90 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32 |
| 文件页数： | 124/162页 |
| 文件大小： | 1149K |
| 代理商： | M34518E8SP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页当前第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页
Rev.3.01
2005.06.15
page 62 of 157
REJ03B0008-0301
4518 Group
RAM BACK-UP MODE
The 4518 Group has the RAM back-up mode.
When the EPOF and POF instructions are executed continuously,
system enters the RAM back-up state. The POF instruction is
equal to the NOP instruction when the EPOF instruction is not ex-
ecuted before the POF instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM. Table 18 shows the function
and states retained at RAM back-up. Figure 53 shows the state
transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (re-
turn from the normal reset state) can be identified by examining the
state of the RAM back-up flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF and POF instruc-
tions continuously, the CPU starts executing the program from
address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
reset pulse is input to RESET pin, or
reset by watchdog timer is performed, or
voltage drop detection circuit detects the voltage drop, or
SRST instruction is executed.
In this case, the P flag is “0.”
Table 18 Functions and states retained at RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Interrupt control registers V1, V2
Interrupt control registers I1, I2
Selection of oscillation circuit
Clock control register MR
Timer 1 function
Timer 2 function
Timer 3 function
Timer 4 function
Watchdog timer function
Timer control register PA, W4
Timer control registers W1 to W3, W5, W6
Serial I/O function
Serial I/O mode register J1
A/D conversion function
A/D control registers Q1 to Q3
Voltage drop detection circuit
Port level
Key-on wakeup control register K0 to K2
Pull-up control registers PU0, PU1
Port output direction registers FR0 to FR2
External 0 interrupt request flag (EXF0)
External 1 interrupt request flag (EXF1)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Timer 3 interrupt request flag (T3F)
Timer 4 interrupt request flag (T4F)
A/D conversion completion flag (ADF)
Serial I/O transmission/reception completion flag
(SIOF)
Interrupt enable flag (INTE)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
RAM back-up
O
O
(Note 3)
(Note 4)
O
O
O
O (Note 5)
O
(Note 3)
(Note 4)
Notes 1:“O” represents that the function can be retained, and “” repre-
sents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction, and then
execute the POF instruction.
5: The valid/invalid of the voltage drop detection circuit can be con-
trolled only by VDCE pin.
相关PDF资料 |
PDF描述 |
|---|---|
| M34518M2-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP32 |
| M34519M6-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| M34519M8-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| M34519E8FP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| M34519M8-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M34518M2-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34518M2-XXXSP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34518M4-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34518M4-XXXSP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34518M6-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
发布紧急采购，3分钟左右您将得到回复。