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参数资料
| 型号： | M37270EF-XXXSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP64 |
| 封装： | 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64 |
| 文件页数： | 19/97页 |
| 文件大小： | 1359K |
| 代理商： | M37270EF-XXXSP |
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MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
23
A-D control register
(ADCON: address 00EF16)
A-D conversion completion bit
0 : Conversion in purogress
1 : Conversion completed
Analog input pin selection bits
b1 b0
0 0 : P26/AD1
0 1 : P25/AD2
1 0 : P24/AD3
1 1 : P40/AD4
VCC connection selection bit
0 : OFF
1 : ON
Fix this bit to “0.”
0
7
A-D CONVERTER
(1)A-D Conversion Register (AD)
A-D conversion reigister is a read-only register that stores the result
of an A-D conversion. This register should not be read during A-D
conversion.
(2)A-D Control Register (ADCON)
The A-D control register controls A-D conversion. Bits 1 and 0 of this
register select analog input pins. When these pins are not used as
anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D
conversion completion bit, A-D conversion is started by writing “0” to
this bit. The value of this bit remains at “0” during an A-D conversion,
then changes to “1” when the A-D conversion is completed.
Bit 4 controls connection between the resistor ladder and VCC. When
not using the A-D converter, the resistor ladder can be cut off from
the internal VCC by setting this bit to “0.” This can realize the low-
power dissipation.
(3)Comparison Voltage Generator (Resistor
Ladder)
The voltage generator divides the voltage between VSS and VCC by
256, and outputs the divided voltages to the comparator as the refer-
ence voltage Vref.
(4)Channel Selector
The channel selector connects an analog input pin selected by bits 1
and 0 of the A-D control register to the comparator.
(5)Comparator and Control Circuit
The conversion result of the analog input voltage and the reference
voltage “Vref” is stored in the A-D conversion register. The A-D con-
version completion bit and A-D conversion interrupt request bit are
set to “1” at the completion of A-D conversion.
Fig. 16. A-D comparator block diagram
Fig. 15. Structure of A-D control register
A-D control register
(
address 00EF16)
A-D control circuit
Data bus
Switch tree
A-D conversion
interrupt request
Resistor ladder
Compa-
rator
Channel
selector
A-D conversion register
P26/AD1
P25/AD2
P24/AD3
P40/AD4
(
address 00EE16)
b7
b0
2
8
VSS VCC
0
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