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| 型号： | M37270EF-XXXSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP64 |
| 封装： | 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64 |
| 文件页数： | 33/97页 |
| 文件大小： | 1359K |
| 代理商： | M37270EF-XXXSP |
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MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
36
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at
φ = 4 MHz)
Table 6. Multi-master I2C-BUS interface functions
Item
Format
Communication mode
SCL clock frequency
φ : System clock = f(XIN)/2
Note: We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the con-
trol function (bits 6 and 7 of the I2C control register at address
00F916) for connections between the I2C-BUS interface and
ports (SCL1, SCL2, SDA1, SDA2).
MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a circuit for serial communica-
tions conformed with the Philips I2C-BUS data transfer format. This
interface, having an arbitration lost detection function and a synchro-
nous function, is useful for serial communications of the multi-mas-
ter.
Figure 36 shows a block diagram of the multi-master I2C-BUS inter-
face and Table 6 shows multi-master I2C-BUS interface functions.
This multi-master I2C-BUS interface consists of the I2C address reg-
ister, the I2C data shift register, the I2C clock control register, the I2C
control register, the I2C status register and other control circuits.
Fig. 36. Block diagram of multi-master I2C-BUS interface
I C address register
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Noise
elimination
circuit
Serial
data
(SDA)
Address comparator
b7
I C data shift register
b0
Data
control
circuit
I C clock control register
System clock
(
φ )
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
MST TRX BB PIN
AL AAS AD0 LRB
b0
I C status
register
S1
b7
b0
BSEL1 BSEL0 10BIT
SAD
ALS
BC2 BC1 BC0
S1D I C clock control register
Bit counter
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
Serial
clock
(SCL)
b7
b0
ACK ACK
BIT
FAST
MODE
CCR4 CCR3 CCR2 CCR1 CCR0
Internal data bus
Clock division
S0
S2
S0D
AL
circuit
ES0
2
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