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参数资料
| 型号： | M37270EF-XXXSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP64 |
| 封装： | 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64 |
| 文件页数： | 20/97页 |
| 文件大小： | 1359K |
| 代理商： | M37270EF-XXXSP |
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MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
24
12 3 45 6 7 8
1 0000 0 0 0
12
100
0 0
0
1000
0 0
0
1
1 2 3 4 567 1
VREF
2
VREF
512
–
VREF
2
VREF
4
VREF
512
–
±
VREF
2
VREF
4
VREF
8
VREF
512
±
0 0000
0 0
0
Contents of A-D conversion register
Reference voltage (Vref)
[V]
0
A-D conversion start
1st comparison start
3rd comparison start
8th comparison start
2nd comparison start
Digital value corresponding to
analog input voltage.
A-D conversion completion
(8th comparison completion)
VREF
2
VREF
4
VREF
8
±
VREF
512
VREF
256
.......
Value determined by mth (m = 1 to 8) result
m
.....
VREF
256
! (n – 0.5)
1 to 255
0
Note: VREF indicates the voltage of internal VCC.
Fig. 17. Changes in A-D conversion register and comparison voltage during A-D conversion
(6) Conversion Method
Set bit 7 of the interrupt interval determination control register (ad-
dress 021216) to “1” to generate an interrupt request at comple-
tion of A-D conversion.
Set the A-D conversion INT3 interrupt request bit to “0” (even
when A-D conversion is started, the A-D conversion INT3 inter-
rupt bit is not set to “0” automatically).
When using A-D conversion interrupt, enable interrupts by setting
A-D conversion INT3 interrupt request bit to “1” and setting the
interrupt disable flag to “0.”
Set the VCC connection selection bit to “1” to connect VCC to the
resistor ladder.
Select analog input pins by setting the analog input selection bit of
the A-D control register.
Set the A-D conversion completion bit to “0.” This write operation
starts the A-D conversion. Do not read the A-D conversion regis-
ter during the A-D conversion.
Verify the completion of the conversion by the state (“1”) of the
A-D conversion completion bit, that (“1”) of A-D conversion INT3
interrupt bit, or the occurrence of an A-D conversion interrupt.
Read the A-D conversion register to obtain the conversion results.
Note : When the ladder resistor is disconnect from VCC, set the VCC
connection selection bit to “0” between steps and .
Table 2. Expression for Vref and VREF
A-D conversion register contents “n”
(decimal notation)
Vref (V)
(7) Internal Operation
At the time when the A-D conversion starts, the following operations
are automatically performed.
The A-D conversion register is set to “0016.”
The most significant bit of the A-D conversion register becomes
“1, ” and the comparison voltage “Vref” is input to the comparator.
At this point, Vref is compared with the analog input voltage “VIN .”
Bit 7 is determined by the comparison result as follows.
When Vref < VIN : bit 7 holds “1”
When Vref > VIN : bit 7 becomes “0”
With the above operations, the analog value is converted into a digi-
tal value. The A-D conversion terminates in a maximum 50 machine
cycles (12.5
s at f(XIN) = 8 MHz) after it starts, and the conversion
result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time of A-D
conversion completion, the A-D conversion INT3 interrupt request
bit becomes “1.” The A-D conversion completion bit also becomes
“1.”
:
±
–
±
–
0
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