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参数资料
| 型号： | M37546G2SP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封装： | 8.90 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32 |
| 文件页数： | 104/105页 |
| 文件大小： | 1105K |
| 代理商： | M37546G2SP |
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REJ03B0160-0122 Rev.1.22 Mar 13, 2009
page 96 of 100
7546 Group
Notes on Input Capture
1. If the capture trigger is input while the capture register (low-or-
der and high-order) is in read, captured value is changed
between high-order reading and low-order reading. Accordingly,
some countermeasure by program is recommended, for ex-
ample comparing the values that twice of read.
2. Timer A cannot be used for the capture source timer in the fol-
lowing state;
XIN oscillation selected by clock division ratio selection bits
(bits 7 and 6 of CPU mode register (address 003B16))
Timer A count source: On-chip oscillator output.
Timer B cannot be used for the capture source timer in the fol-
lowing state;
XIN oscillation selected by clock division ratio selection bits
Timer B count source: Timer A underflow
Timer A count source: On-chip oscillator output.
3. As shown below, when the capture input is performed to both
capture latch 00 and 01 at the same time, the value of capture
0 status bit (bit 4 of capture/compare status register (address
002216)) is undefined (same as capture 1).
When “1” is written to capture latch 00 software trigger bit (bit 0
of capture software trigger register (address 001316)) and cap-
ture latch 01 software trigger bit (bit 1 of capture software trigger
register) at the same time
When external trigger of capture latch 00 and software trigger of
capture latch 01 occur at the same time
When external trigger of capture latch 01 and software trigger of
capture latch 00 occur at the same time
4. When the capture interrupt is used as the interrupt for return
from stop mode, set the capture 0 noise filter clock selection
bits (bits 5 and 4 of capture mode register (address 002016)) to
“00 (Filter stop)” (same as capture 1).
Notes on Serial I/Oi (i=1, 2)
1. Clock synchronous serial I/O
(1) When the transmit operation is stopped, clear the serial I/Oi
enable bit and the transmit enable bit to “0” (serial I/Oi and
transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/Oi enable bit is cleared to “0”
(serial I/Oi disabled), the internal transmission is running (in this
case, since pins TxDi, RxDi, SCLKi, and SRDYi function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/Oi enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxDi pin and an operation failure occurs.
(2) When the receive operation is stopped, clear the receive en-
able bit to “0” (receive disabled), or clear the serial I/Oi enable
bit to “0” (serial I/Oi disabled).
(3) When the transmit/receive operation is stopped, clear both the
transmit enable bit and receive enable bit to “0” (transmit and
receive disabled) simultaneously. (any one of data transmis-
sion and reception cannot be stopped.)
<Reason>
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception.
If any one of transmission and reception is disabled, a bit error oc-
curs because transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also oper-
ates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit cannot be initialized even
if the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled)
(same as (1)).
(4) When signals are output from the SRDYi pin on the reception
side by using an external clock, set all of the receive enable
bit, the SRDYi output enable bit, and the transmit enable bit to
“1”.
(5) When the SRDYi signal input is used, set the using pin to the in-
put mode before data is written to the transmit/receive buffer
register.
2. UART
When the transmit operation is stopped, clear the transmit enable
bit to “0” (transmit disabled).
<Reason>
Same as (1) shown on the above “1. Clock synchronous serial I/O“.
When the receive operation is stopped, clear the receive enable
bit to “0” (receive disabled).
When the transmit/receive operation is stopped, clear the transmit
enable bit to “0” (transmit disabled) and receive enable bit to “0”
(receive disabled).
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相关代理商/技术参数 |
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| M37546G2SP#U0 | 功能描述:MCU 3/5V 8K 32-SDIP QZ-ROM RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 标准包装:250 系列:80C 核心处理器:8051 芯体尺寸:8-位 速度:16MHz 连通性:EBI/EMI，I²C，UART/USART 外围设备:POR，PWM，WDT 输入/输出数:40 程序存储器容量:- 程序存储器类型:ROMless EEPROM 大小:- RAM 容量:256 x 8 电压 - 电源 (Vcc/Vdd):4.5 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-LCC（J 形引线） 包装:带卷 (TR) |
| M37546G2-XXXGP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37546G2-XXXHP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37546G2-XXXSP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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