参数资料
型号: M38D24G6-XXXFP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
封装: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件页数: 65/136页
文件大小: 2856K
代理商: M38D24G6-XXXFP
Rev.3.02
Apr 10, 2008
Page 34 of 131
REJ03B0177-0302
38D2 Group
16-bit Timer
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write
the low-order byte first. The 16-bit timer cannot perform the
correct operation when reading during the write operation, or
when writing during the read operation.
Fig. 26 Timer X block diagram
Data bus
1/2
1/4
Frequency
divider
Noise filter sampling
clock selection bit
“1”
“0”
Timer X interrupt
request
Timer X (high-order)(8)
Timer X (low-order)(8)
Timer X(high-order) latch (8)
Timer X (low-order) latch (8)
Equal
“000”
“001”
“010”
“011”
“101”
Pulse width
measurement
mode
Timer X count
stop bit
INT2
CNTR0 active
edge switch bits
Timer X operating
mode bits
CNTR0
interrupt request
“100”
Extend latch (2)
Timer X write
control bit
Timer 1 interrupt
D Q
Latch
Data for control of event counter window
CNTR0
INT0
0
μs
Delay time
selection bits
4/f(XIN)
“00”
“01”
“10”
“11”
8/f(XIN)
16/f(XIN)
Noise filter
(4 times same
levels judgment)
INT0
interrupt request
Count source selection bit
XcIN
“1”
“0”
Clock for timer X
XIN
Frequency divider
Timer X frequency
division selection bits
2
Both edges
detection
“00”
“01”
“10”
“11”
Timer X output
control bit 1
Timer X output
control bit 2
Timer X operating
mode bits
“010”
Delay
circuit
“000”
“001”
“011”
“100”
“101”
Timer X operating
mode bits
“010”
Compare register 3 (low-order)(8) Compare register 3 (high-order)(8)
Compare register 1 (low-order)(8) Compare register 1 (high-order)(8)
Compare register 2 (low-order)(8) Compare register 2 (high-order)(8)
Q
T
S
Pulse output mode
Timer X output 1
selection bit
P35
latch
P35
direction
register
P35/TXOUT1/(LED5)
Q
T
R
Timer X output 1
edge switch bit
“0”
“1”
IGBT output mode
PWM mode
Q
T
R
Timer X output 2
selection bit
P37
latch
P37
direction
register
P37/CNTR0/TXOUT2/(LED7)
Timer X output 2
edge switch bit
“0”
“1”
Extend counter (2)
φSOURCE
φSOURCE : represents the supply source of internal clock φ.
XIN input: in the frequency/2, 4 or 8 mode, Internal
on-chip oscillator divided by 4 in the on-chip
oscillator mode, and Sub clock in the low-speed
mode.
“0”
“1”
Delay circuit 1/2
“1”
“0”
× 2
Trigger for IGBT control bit
INT1
Edge
selection
Edge
selection *
Edge
selection *
Edge
detection
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