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参数资料
| 型号： | M390S1723DTU-C7A |
| 元件分类： | DRAM |
| 英文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封装： | DIMM-168 |
| 文件页数： | 3/12页 |
| 文件大小： | 188K |
| 代理商： | M390S1723DTU-C7A |
M390S1723DTU
Rev. 0.1. Sept. 2001
PC133/PC100 Low Profile Registered DIMM
Byte #
Function described
Function Supported
Hex value
Note
-7C
-7A
-1H
-1L
-7C
-7A
-1H
-1L
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
12
0Ch
1
4
# of column address on this assembly
10
0Ah
1
5
# of module Rows on this assembly
1
row
01h
6
Data width of this assembly
72 bits
48h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time from clock @CAS latency of 3
7.5ns
10ns
75h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
5.4ns
6ns
54h
60h
2
11
DIMM configuration type
ECC
02h
12
Refresh rate & type
15.625us, support self refresh
80h
13
Primary SDRAM width
x8
08h
14
Error checking SDRAM width
x8
08h
15
Minimum clock delay for back-to-back random column address
tCCD = 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Registered/Buffered DQM,
address & control inputs and
On-card PLL
1Fh
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
7.5ns
10ns
12ns
75h
A0h
C0h
2
24
SDRAM access time @CAS latency of 2
5.4ns
6ns
7ns
54h
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
00h
26
SDRAM access time @CAS latency of 1
-
00h
27
Minimum row precharge time (=tRP)
15ns
20ns
0Fh
14h
28
Minimum row active to row active delay (tRRD)
15ns
20ns
0Fh
14h
29
Minimum RAS to CAS delay (=tRCD)
15ns
20ns
0Fh
14h
30
Minimum activate precharge time (=tRAS)
45ns
50ns
2Dh
32h
31
Module Row density
1 Row of 128MB
20h
32
Command and Address signal input setup time
1.5ns
2ns
15h
20h
33
Command and Address signal input hold time
0.8ns
1ns
08h
10h
34
Data signal input setup time
1.5ns
2ns
15h
20h
M390S1723DTU-C7C/C7A/C1H/C1L
Organization : 16MX72
Composition : 16MX8 * 9ea
Used component part # : K4S280832D-TC7C/75/C1H/C1L
# of rows in module : 1 Row
# of rows in component : 4 banks
Feature : 1,200 mil height & double sided
Refresh : 4K/64ms
Contents :
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相关代理商/技术参数 |
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| M390S2858CT1 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:SDRAM DIMM |
| M390S2858CT1-C7A | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:SDRAM DIMM |
| M390S2858CT1-C7C | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:SDRAM DIMM |
| M390S2858CTU | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:PC133/PC100 Low Profile Registered DIMM |
| M390S2858CTU-C1H | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:PC133/PC100 Low Profile Registered DIMM |
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