参数资料
型号: M390S1723DTU-C7A
元件分类: DRAM
英文描述: 16M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168
封装: DIMM-168
文件页数: 7/12页
文件大小: 188K
代理商: M390S1723DTU-C7A
M390S1723DTU
Rev. 0.1. Sept. 2001
PC133/PC100 Low Profile Registered DIMM
td, tr = Delay of register
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register. Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as
compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don
′t care
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
REG
Control Signal(RAS,CAS,WE)
*1
*2
*3 DOUT
*1. Register Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
RAS
CAS
WE
RAS
CAS
WE
tSAC
tRDL
Read
Row Active
Command
Row Active
Write
Command
Precharge
Command
1CLK
td
tr
td
tr
*2. Register Output
*3. SDRAM
tRAC(refer to *1)
CAS latency(refer to *1)
=2CLK+1CLK
DQ
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Precharge
Command
CAS latency(refer to *2)
=2CLK
tRAC(refer to *2)
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