参数资料
型号: M52259EVB
厂商: Freescale Semiconductor
文件页数: 39/46页
文件大小: 0K
描述: BOARD EVAL FOR 52259 COLDFIRE V2
产品培训模块: ColdFire MCF5225x
标准包装: 1
系列: ColdFire®
类型: MCU
适用于相关产品: MCF52259
所含物品: 板,线缆,文档,DVD,闪光灯驱动和电源
Electrical Characteristics
Table 25. ADC Parameters 1 (continued)
Name
SNR
THD
SFDR
SINAD
ENOB
Characteristic
Signal-to-noise ratio
Total harmonic distortion
Spurious free dynamic range
Signal-to-noise plus distortion
Effective number of bits
Min
9.1
Typical
62 to 66
? 75
67 to 70.3
61 to 63.9
10.6
Max
Unit
dB
dB
dB
dB
Bits
1
2
3
4
5
6
7
All measurements are preliminary pending full characterization, and made at V DD = 3.3 V, V REFH = 3.3 V, and V REFL = ground
INL measured from V IN = V REFL to V IN = V REFH
LSB = Least Significant Bit
INL measured from V IN = 0.1V REFH to V IN = 0.9V REFH
Includes power-up of ADC and V REF
ADC clock cycles
Current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC
2.16
Equivalent Circuit for ADC Inputs
Figure 14 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is
closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (V REFH -V REFL )/2, while
the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about (V REFH -V REFL )/2. The switches
switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional
capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function
of the analog input voltage, V REF and the ADC clock frequency.
125W ESD Resistor
8pF noise damping capacitor
Analog Input
3
S1
4
S3
C1
S/H
1
2
(V REFH - V REFL )/ 2
S2
C2
C1 = C2 = 1pF
1.
2.
3.
4.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8 pF
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04 pF
Equivalent resistance for the channel select mux; 100 ?
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4 pF
5.
Equivalent input impedance, when the input is selected =
1
(ADC Clock Rate) ? (1.4 ? 10 -12 )
Figure 14. Equivalent Circuit for A/D Loading
MCF52259 ColdFire Microcontroller, Rev. 5
39
Freescale
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