- 您现在的位置：买卖IC网 > Datasheet目录339 > M52259EVB (Freescale Semiconductor)BOARD EVAL FOR 52259 COLDFIRE V2 Datasheet资料下载
参数资料
| 型号： | M52259EVB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 9/46页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR 52259 COLDFIRE V2 |
| 产品培训模块： | ColdFire MCF5225x |
| 标准包装： | 1 |
| 系列： | ColdFire® |
| 类型： | MCU |
| 适用于相关产品： | MCF52259 |
| 所含物品： | 板，线缆，文档，DVD，闪光灯驱动和电源 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页
Family Configurations
1.2.2
V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage
instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is
a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).
The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with support for a separate user stack pointer
register and four new instructions to assist in bit processing. Additionally, the core includes the enhanced multiply-accumulate
(EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic pipeline, optimized
for 32x32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and
unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC
provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.
1.2.3
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator
development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided
on 144-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit
emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,
a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor ’s supervisor mode programming model. The breakpoint
registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or
dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
This device implements revision B+ of the ColdFire Debug Architecture.
The processor ’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be
serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports.
These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining
processor activity at the CPU’s clock rate. The device includes a new debug signal, ALLPST. This signal is the logical AND of
the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 144-pin packages. However, every product features the dedicated debug
serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.4
JTAG
The processor supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action
Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and
three test registers (a 1-bit bypass register, a boundary-scan register, and a 32-bit ID register). The boundary scan register links
the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system
logic.
The device implementation can:
9
?
?
?
?
?
Perform boundary-scan operations to test circuit board electrical continuity
Sample system pins during operation and transparently shift out the result in the boundary scan register
Bypass the device for a given circuit board test by effectively reducing the boundary-scan register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
MCF52259 ColdFire Microcontroller, Rev. 5
Freescale
相关PDF资料 |
PDF描述 |
|---|---|
| M5234BCCKIT | KIT EVALUATION FOR MCF5234 |
| M5253DEMO | DEMO BOARD FOR MCF5253 |
| M57160AL-01 | IC GATE DRVR FOR IGBT MOD |
| M57959L | IC GATE DRVR FOR IGBT MOD |
| M57962CL-01 | IC GATE DRVR FOR IGBT MOD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M52259EVB | 制造商:Freescale Semiconductor 功能描述:MCF5225x Evaluation Board |
| M5226P | 制造商:Panasonic Industrial Company 功能描述:IC |
| M5226PFP | 制造商:MITSUBISHI 制造商全称:Mitsubishi Electric Semiconductor 功能描述:5-ELEMENT GRAPHIC EQUALIZER IC |
| M52277EVB | 功能描述:开发板和工具包 - 其他处理器 EVAL BOARD FOR THE M52277x RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| M5228FP | 制造商:Panasonic Industrial Company 功能描述:IC |
发布紧急采购，3分钟左右您将得到回复。