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参数资料
型号： M7020R-050ZA1T
厂商： 意法半导体
英文描述： CAP TANT 22UF 10V 20% POLY SMD
中文描述： 32K的× 68位进入网络搜索引擎
文件页数： 18/150页
文件大小： 996K
代理商： M7020R-050ZA1T
M7020R
18/150
OPERATION
The following subsections contain command
(CMD and DQ Bus (command and databus), data-
base entry, arbitration logic, pipeline, and SRAM
control, and full logic descriptions.
CMD Bus and DQ Bus
CMD[8:0] carries the CMD and its associated pa-
rameter. DQ[67:0] is used for data transfer to and
from the database entries, which comprise a data
and a mask field that are organized as data and
mask arrays. The DQ Bus carries the SEARCH
data (of the data and mask arrays and internal reg-
isters) during the SEARCH command as well as
the address and data during READ and/or WRITE
operations. The DQ Bus can also carry the ad-
dress information for the flow-through accesses to
the external SRAMs and/or SSRAMs.
Database Entry (Data Array and Mask Array)
Each database entry comprises a data and a mask
field. The resultant value of the entry is ’1,' ’0,’ or
’X (don’t care),’ depending on the value in the data
and mask bits. The on-chip priority encoder se-
lects the first matching entry in the database that
is nearest to location '0.'
Arbitration Logic
When multiple Search Engines are cascaded to
create large databases, the data being searched is
presented to all search engines simultaneously in
the cascaded system. If multiple matches occur
within the cascaded devices, arbitration logic on
the search engines will enable the winning device
(with a matching entry that is closest to address “0”
of the cascaded database) to drive the SRAM bus.
Pipeline and SRAM Control
Pipeline latency is added to give enough time to a
cascaded system’s arbitration logic to determine
the device that will drive the index of the matching
entry on the SRAM bus. Pipeline logic adds laten-
cy to both the SRAM access cycles and the SSF
and SSV signals to align them to the host ASIC re-
ceiving the associated data.
Full Logic
Bit[0] in each of the 68-bit entries has a special
purpose for the LEARN command (0 = empty, 1 =
full). When all the data entries have bit[0] = 1, the
database asserts the FULL Flag, indicating all the
search engines in the depth-cascaded array are
full.
相关PDF资料
PDF描述
M7020R-066ZA1T 32K x 68-bit Entry NETWORK SEARCH ENGINE
M7020R-083ZA1T 32K x 68-bit Entry NETWORK SEARCH ENGINE
M7020R 32K x 68-bit Entry NETWORK SEARCH ENGINE
M72DW64000B 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
M72DW64000B70ZT 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
相关代理商/技术参数
参数描述
M7020R-066ZA1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32K x 68-bit Entry NETWORK SEARCH ENGINE
M7020R-083ZA1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32K x 68-bit Entry NETWORK SEARCH ENGINE
M702-230442 功能描述:火线接头 IEEE 1394 SMT 4P HORIZONTAL RoHS:否 制造商:Molex 产品:IEEE 1394 Firewire Connectors 标准:IEEE 1394 位置/触点数量:6 节距:2 mm 触点电镀:Unplated 触点材料:Phosphor Bronze 型式:Female 电流额定值:0.5 A 安装风格:Through Hole 端接类型:Solder Tab 连接器类型:Firewire Receptacle
M702-230642 功能描述:火线接头 IEEE 1394 SMT 6P HORIZONTAL RoHS:否 制造商:Molex 产品:IEEE 1394 Firewire Connectors 标准:IEEE 1394 位置/触点数量:6 节距:2 mm 触点电镀:Unplated 触点材料:Phosphor Bronze 型式:Female 电流额定值:0.5 A 安装风格:Through Hole 端接类型:Solder Tab 连接器类型:Firewire Receptacle
M7023 制造商:Tamura Corporation of America 功能描述:
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