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参数资料
型号： M7020R-050ZA1T
厂商： 意法半导体
英文描述： CAP TANT 22UF 10V 20% POLY SMD
中文描述： 32K的× 68位进入网络搜索引擎
文件页数： 62/150页
文件大小： 996K
代理商： M7020R-050ZA1T
M7020R
62/150
Table 31. Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, Up to 31 Devices
Table 32. Shift of SSF and SSV from SADR
136-bit Configuration with Single Device
The hardware diagram for this search subsystem
is shown in Figure 41.
Figure 42, page 64 shows the timing diagram for a
SEARCH command in the 136-bit-configured ta-
ble (CFG = 01010101) consisting of a single de-
vice for one set of parameters. This illustration
assumes that the host ASIC has programmed
TLSZ to ’00,’ HLAT to ’001,’ LRAM to ’1,’ and LDEV
to ’1.’
The following is the operation sequence for a sin-
gle 136-bit SEARCH command (refer to COM-
MAND CODES AND PARAMETERS, page 29).
–
Cycle A:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') to
CMD[1:0] signals. CMD[5:3] signals must be
driven with the index to the GMR pair for use in
this SEARCH operation. CMD[8:7] signals must
be driven with the same bits that will be driven
on SADR[21:20] by this device if it has a hit.
DQ[67:0] must be driven with the 68-bit data
([135:68]) to be compared against all even loca-
tions. The CMD[2] signal must be driven to logic
'0.'
–
Cycle B:
The host ASIC continues to drive the
CMDV high and applies the command code of
SEARCH command ('10') on CMD[1:0].
CMD[5:2] must be driven by the index of the
comparand register pair for storing the 136-bit
word presented on the DQ Bus during Cycles A
and B. CMD[8:6] signals must be driven with the
index of the SSR that will be used for storing the
address of the matching entry and Hit Flag (see
SEARCH-Successful
page 23). The DQ[67:0] is driven with 68-bit
data ([67:0]), compared to all odd locations.
Note:
For 136-bit searches, the host ASIC must
supply two distinct 68-bit data words on
DQ[67:0] during Cycles A and B. The even-
numbered GMR of the pair specified by the
GMR Index is used for masking the word in Cy-
cle A. The odd-numbered GMR of the pair spec-
ified by the GMR Index is used for masking the
word in Cycle B.
Registers
(SSR[0:7]),
# of devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
32K x 68-bit
4
2–8 (TLSZ = 01)
256K x 68-bit
5
9–31 (TLSZ = 10)
992K x 68-bit
6
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
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相关代理商/技术参数
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