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| 型号： | MA17501 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | Radiation Hard MIL-STD-1750A Execution unit |
| 中文描述： | 辐射硬的MIL - STD - 1750A执行单元 |
| 文件页数： | 12/35页 |
| 文件大小： | 431K |
| 代理商： | MA17501 |
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MA17501
12/35
Operand transfers use the address register (A), data input
register (Dl), and data output register (DO). Before the
operand transfer begins, the Execution Unit calculates the
effective operand address and stores this value in A.
For write transfers the EU loads the operand into DO. For
operand ready cycles the EU latches the operand from the AD
Bus into Dl at the SYSCLK1N high-to-low transition.
All operand transfers between the MAS281 and memory
are referenced to the AS and DSN bus control signals and are
characterised by lN/OPN low, M/lON and CDN high, and RD/
WN (high, read; low, write).
The EU first places the contents of A on the AD Bus at the
SYSCLK1N high-to-low transition. Shortly following, AS is
raised high to enable the system address bus transparent
latch. This address is assured valid at the high-to-low transition
of AS. At the SYSCLK1N low-to high transition, DSN drops low
to indicate the contents of DO have been placed on the AD
Bus (write) or the EU AD Bus drivers have been placed in the
high impedance state (read).
DSN subsequently raises high when the output data is
stable, prior to SYSCLK1N dropping low, or raises high in
response to SYSCLK1N dropping low to indicate the EU's
acceptance of the input data.
All operand transfer cycles are allowed to complete via the
RDYN input. During the data portion of the cycle the EU
assumes memory is NOT READY, and requires RDYN low to
signal the memory’s readiness to complete the cycle. If RDYN
is high at the high-to-low transition of the fifth OSC cycle within
the operand transfer cycle, a wait state will be injected (one
OSC period at a time) for each OSC high-to-low transition that
RDYN remains high. Memory readiness, thus cycle
completion, is signalled by RDYN low enveloping a
subsequent OSC high-to-low transition.
4.2.4 Input/Output Transfers
Input/Output transfers are characterised by M/lON and IN/
OPN low, and RD/WN (high, input; low, output). AS and DSN
operate as during operand transfers. Two different types of
input/output transfers are controlled by the Execution Unit:
internal and external.
Internal l/O transfers involve all XlO commands that are
decoded by the lnterrupt Unit (lU) and use the local AD Bus to
transfer response data. These commands are listed in Table 3
(the only exception is RCW; it is an lU decoded, lRDYN
completed, External l/O command). Internal XlO commands
implemented in the lU (per Table 3) use a six OSC period
machine cycle and the IRDYN cycle completion input. lnternal
XlO commands implemented in the MA31751 MMU/BPU use
a minimum five OSC period machine cycle. The system RDYN
generator provides the RDYN cycle completion input to the
EU.
The term "local AD Bus" in this context refers to the AD Bus
on the processor side of the system data bus demultiplexing
transceivers. The three chips of the MAS281 and the
MA17504 (in either configuration) reside on the local AD Bus
and communicate to the user system through the required
address and data bus buffers, as depicted in Figure 4.
External I/O transfers involve all XlO and VlO instructions
not included under lnternal l/O transfers. They execute during
a minimum five OSC period machine cycle that is extendible
via RDYN, as previously described.
4.3 INTERRUPT SERVICING
Interrupts are latched into the lnterrupt Unit (lU) pending
interrupt register by the SYNCLKN high-to-low transition. The
lU signals the Control Unit (CU) that an interrupt is pending
and the CU branches to the microcoded interrupt handling
routine at the completion of the currently executing MlL-STD-
1750A instruction.
The EU supports the interrupt handling routine by enabling
microcode control of the lU at the proper time via the lNTREN
signal and by calculating the memory addresses of the service
and linkage pointers based on the 4-bit interrupt priority code
transmitted by the IU. Machine cycles during which lNTREN is
low are six OSC periods in length. During these lNTREN
cycles, DSN and M/lON are high, and AS is low.
The EU also provides a hardwired interrupt to the lU. the
OVIN interrupt signals a fixed-point arithmetic overflow.
4.4 FAULT SERVICING
The Interrupt Unit (IU) latches fault inputs into the fault
register on the high-to-low transition of SYNCLKN. Faults other
than 0, 5, and 8 latch a level one pending interrupt in the lU and
the interrupt sequencing proceeds as previously explained.
Faults 0, 5, and 8 caused during non-DMA AD Bus transactions
demand more immediate attention; the MlL-STD-1750A
instruction during which the fault occurred must be aborted.
PIFN indicates to the Control Unit that one of these faults
has occurred and forces a branch to the “next instruction fetch’’
microinstruction so that the interrupt caused by the PlFN fault
can be serviced immediately. Under normal instruction
execution circumstances, the bus control signals would operate
during the machine cycle between the fault and the instruction
fetch machine cycle. PlFN causes the bus control signals AS
and DSN to stay in their inactive state during this transitional
machine cycle to allow the branch to the microcoded interrupt
routine without performing any AD Bus transactions.
4.5 DIRECT MEMORY ACCESS
The Interrupt Unit DMA interface logic signals the
Execution Unit (EU) that it has acknowledged a DMA request
(PAUSEN low). PAUSEN low causes the EU to halt the
synchronisation clocks CLK02N (high), CLKPCN (low), and
SYSCLK1N (low); disables clock generation circuitry input that
could vary the machine cycle length; and places all bus control
signals and the AD Bus in the high impedance state. The
SYNCN and SYNCLKN clocks continue to operate with a five
OSC cycle period. Upon removal of PAUSEN by the Interrupt
Unit, the MAS281 resumes microinstruction execution where it
was interrupted.
4.6 SOFTWARE DEVELOPMENT SUPPORT
The Execution Unit responds to a HOLDN signal by
suspending all internal operations upon completion of the
currently executing instruction. Microcode, from the Control
Unit, directs HLDAKN low during the third SYNCN cycle after
HOLDN has been pulled low and the previous instruction has
been completed. M/lON, RD/WN, IN/OPN, AS, DSN, and the
AD Bus are placed in the high impedance state permitting a
monitor system to take control of the memory/input-output
system. Raising HOLDN releases the MAS281 from the Hold
state and instruction execution begins by refilling the pipeline.
The execution of a BPT instruction also causes HLDAKN
to drop low and the bus control signals and AD Bus to be
placed in the high impedance state. A low pulse on HOLDN
releases the MAS281 from the BPT initiated Hold state.
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相关代理商/技术参数 |
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| MA17502 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:Radiation Hard MIL-STD-1750A Control Unit |
| MA17503 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:Radiation Hard MIL-STD-1750A Interrupt Unit |
| MA1751E12B1+6-FSR-EM | 制造商:Mechatronics Fan Group 功能描述: |
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| MA1751E24B-FSR | 功能描述:AXIAL FAN 172X150X51MM 24VDC 制造商:mechatronics fan group 系列:* 零件状态:在售 标准包装:1 |
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