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参数资料
型号： MA17501
厂商： Dynex Semiconductor Ltd.
英文描述： Radiation Hard MIL-STD-1750A Execution unit
中文描述： 辐射硬的MIL - STD - 1750A执行单元
文件页数： 26/35页
文件大小： 431K
代理商： MA17501
MA17501
26/35
No.
Parameter
Test Conditions (1) (2)
Min (2)
Typ (2)
Max (2)
Units
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
OSC
↑
to SYNCN
OSC
↑
to SYSCLK1N
OSC
↑
to SYNCLKN
OSC
↑
to CLKPCN
OSC
↑
to CLK02N
SYNCN
↓
to AS
↑
SYNCN
↓
to AS
↓
(4)
SYNCN
↓
to DSN (Read)
SYNCN
↓
to DSN
↓
(Read) (3)
SYNCN
↓
to DSN
↓
(Write)
SYNCN
↓
to DSN
↑
(Write) (3)
SYNCN
↓
to Address Valid
SYNCN
↓
to Data Valid
SYNCN
↓
to M/ION, RD/WN, IN/OPN, INTREN Valid
SYNCN
↓
to HLDAKN Valid
SYSCLKN1
↓
to T1 Valid
SYSCLKN1
↓
to OVIN Valid
SYNCN
↓
to AD Bus Hi-Z (Read) (6)
SYNCN
↓
to AD Bus Active (Read)
PAUSEN
↓
to AD Bus Hi-Z (Read) (6)
PAUSEN
↑
to AD Bus Valid
PAUSEN
↓
to AS, DSN, M/ION, RD/WN, IN/IOPN Hi-Z (6)
PAUSEN
↑
to AS, DSN, M/ION, RD/WN, IN/IOPN Valid
HLDAKN
↓
to AD Bus Hi-Z (Read) (6)
HLDAKN
↑
to AD Bus Valid
HLDAKN
↓
to AS, DSN, M/ION, RD/WN, IN/IOPN Hi-Z (6)
HLDAKN
↑
to AS, DSN, M/ION, RD/WN, IN/IOPN Valid
Address after SYNCN
↓
Data after SYNCN
↓
M/ION, RD/WN, IN/OPN, INTREN after SYNCN
HLDAKN after SYNCN
↓
T1N after SYSCLK1N
↓
OVIN after SYSCLK1N
↓
Data to SYNCN
↓
Microcode to CLK02N
↓
Microcode to SYSCLK1N
↓
RDYN to OSC
↓
IRDYN to OSC
↓
Data after SYNCN
↓
Microcode after CLK02N
↓
Microcode after SYSCLK1N
↓
RDYN after OSC
↓
IRDYN after OSC
↓
SYNCN to SYNCN
↓
(7)
RESET
↑
to RESET
↓
(7)
RESET
↑
to Related Outputs Valid (7)
PIFN to Related Outputs Valid
HOLDN to Related Outputs Valid (7)
DSN to Data Valid (Write) (7)
SYNCN to SYNCLKN (No.1 - No.3)
CLKPCN to SYNCLKN (No.4 - No.3)
SYSCLK1 to CLKPC (No.2 - No.4)
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
Load 2
Load 2
Load 2
Load 2
Load 2, 3
Load 2, 3
Load 2
Load 2
Load 2, 3
Load 2, 3
Load 1
Load 1
Load 1
Load 1
Load 1
Load 1
10
40
40
40
40
40
1
τ
+5
2.5
τ
+15
3
τ
+20
30
3
τ
+22
4.5
τ
+10
68
3
τ
+45
70
20
75
100
3
τ
+50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
τ
-10
2.5
τ
-10
3
τ
-5
10
3
τ
-5
4.5
τ
-5
15
70
60
50
59
60
50
30
30
3
τ
+15
12
5
-7
15
20
20
10
10
15
15
0
5
15
5
10
5
τ
-2
2
5
τ
+2
50
50
50
Load 3 (DSN) Load 2 (Data)
15
-5
-5
-5
8
5
10
MIL-STD-883, Method 5005, Subgroup 9, 10, 11
Notes:
1. T
= +25
°
C, -55
°
C and +125
°
C tested at VDD = 4.5V and 5.5V
2. r = 1OSC period 0.5r implies 50% OSC duty cycle
3. Add 1r for internal XlO; nr for memory wait
4. Excluding DMA and Hold conditions
5. Unless otherwise noted: V
ll
=
≥
0.0V, V
IHTTL
≤
4.0V, VIHOSC = 4.0V timing measured from 50% to 50% points
6. High impedance measured by 20% (of VDD) voltage change using 1K-ohm pullup resistor
7. Data obtained by characterisation or analysis, not routinely measured
8. Load 2 applies to bus interface signals AS, RD/W and IN/OP; Load 3 applies to bus interface signals M/ION and DSN
Table 4b: Timing Parameter Values
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