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| 型号： | MA17501 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | Radiation Hard MIL-STD-1750A Execution unit |
| 中文描述： | 辐射硬的MIL - STD - 1750A执行单元 |
| 文件页数： | 9/35页 |
| 文件大小： | 431K |
| 代理商： | MA17501 |
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MA17501
9/35
3.5.1 Processor Pause (PAUSEN)
lnput. PAUSEN is driven low by the lnterrupt Unit upon
acknowledgement of a DMA transfer request. A low on
PAUSEN causes the EU to place all the bus control signals
(AS, DSN, M/lON, RD/WN, IN/OPN) and the AD Bus in the
high impedance state, and to disable all clock outputs, except
for SYNCLKN and SYNCN. The requesting device maintains
control of the AD Bus and bus control lines until (lU)DMARN is
raised high, thus causing PAUSEN to raise high.
lt is recommended that the MAS281 chip set be buffered to
the memory/input-output system. lf an MMU(BPU) peripheral
chip is used for memory expansion/protection it must reside on
the MAS281 side of these buffer transceivers (see Figure 4).
Thus, for a DMA device to access the MMU(BPU), the
MAS281 AD Bus and bus control signal drivers must be in the
high impedance state to allow the DMA device to drive these
signals. The interrupt Unit also provides the CDN signal for the
directional control of the bus control transceivers.
3.5.2 Processor Hold Request (HOLDN)
lnput. A low on this input suspends all chip set functions
(except SYNCN and SYNCLKN) at the end of the current MlL-
STD-1750A instruction. The AD Bus and bus control functions
(AS, DSN, M/ION, lN/OPN, RD/WN) are placed in the high
impedance state permitting a monitor system to take control of
the memory/input-output system. The internal synchronisation
clocks are placed in an inactive state, which halts further
instruction sequencing until HOLDN is released. As with DMA
cycles, the reason for this is to allow access to the MMU(BPU)
if an expanded memory system is used. The (lU)CDN output is
provided for control bus transceiver directional control during
the Hold state. This input should be synchronised to AS falling.
3.4.2 Microcontrol Bus (M Bus)
Input. The M Bus is a 20-bit multiplexed microcontrol bus
which provides microcoded control to the EU. The Control Unit
multiplexes the 40-bit microcode instructions into two 20-bit
words. The upper 20 bits are placed on the M Bus by the
CLKPCN low-to-high transition and the lower 20 bits are
placed on the M Bus by the trailing high-to-low transition of
CLK02N. The microinstruction is reassembled in the EU’s
Execution (E) register and used to control EU functions during
the next machine cycle. M19 is the most significant bit position
and M00 is the least significant bit position for both
microwords. The high order 20 bits are transmitted first,
followed by the low order 20 bits of the microinstruction. A high
on this bus corresponds to a logic one and low corresponds to
a logic zero.
3.5 SYSTEM SUPPORT INTERFACE
The system support interface signals have control over
functions that affect the chip set as a whole.
3.5.3 Processor Hold Acknowledge (HLDAKN)
Output. HLDAKN drops low after reaching the end of the
MIL-STD-1750A instruction during which HOLDN was pulled
low, or after encountering a BPT software instruction. The Hold
state is terminated by raising HOLDN high (if HOLDN low
initiated the Hold state), or by pulsing HOLDN low (if the Hold
state was initiated by a BPT instruction). During the Hold state,
software execution is suspended and the MAS281 interface
functions are placed in the high impedance state to allow a
monitor system to take control of the memory/input-output
system.
3.6 INTER-CHIP CONTROL
The following signals perform control functions internal to
the MAS281 chip set. These functions include microcode
execution branching control and arithmetic error indication.
3.6.1 Internal Ready (IRDYN)
Input. The IRDYN signal is the means by which Interrupt
Unit (IU) command cycles, involving the AD Bus, are
completed. The lU drops lRDYN low when the XlO command
has been decoded and allows the six OSC period machine
cycle to complete. The IRDYN and RDYN signals are
effectively ORed together to control the EU clock generation
circuitry; therefore, RDYN should be high during lU decoded
XlO commands.
3.6.2 Interrupt Unit Microinstruction Enable (INTREN)
Output. The Execution Unit controls the lnterrupt Unit (lU)
3-bit microcode interface through the use of the INTREN
signal. lNTREN low enables the lU microcode decoding logic.
lU functions handled through microcode are; enable/disable
DMA interface XlO command control, set Normal Power-Up
discrete, load fault register, and read encoded 4-bit vector
identifying the highest priority pending interrupt.
Machine cycles during lNTREN low are a special case of
internal non-AD Bus operations. These cycles are denoted by
a six OSC period machine cycle.
3.6.3 Overflow Indicator (OVIN)
Output. OVlN is an indication that a fixed-point overflow
condition, as specified in MIL-STD-1750A, has occurred
during an operation. The Interrupt Unit accepts this as an input
to the pending interrupt register level four interrupt bit.
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相关代理商/技术参数 |
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| MA17502 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:Radiation Hard MIL-STD-1750A Control Unit |
| MA17503 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:Radiation Hard MIL-STD-1750A Interrupt Unit |
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