参数资料
型号: MAX1148BEUP+T
厂商: Maxim Integrated Products
文件页数: 11/25页
文件大小: 0K
描述: IC ADC 14BIT 116KSPS 20-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 14
采样率(每秒): 116k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 879mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
输入数目和类型: 8 个单端,单极;8 个单端,双极;4 个差分,单极;4 个差分,双极
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________
19
Method 1 allows the direct application of an external
reference from 1.5V to VDD + 50mV. The REF input
impedance is typically 10k
. During conversion, an
external reference at REF must deliver up to 210A and
have an output impedance less than 10
. Bypass REF
with a 0.1F capacitor to AGND to improve its output
impedance.
Method 2 utilizes the internal reference buffer to reduce
the external reference load. The REFADJ input imped-
ance is typically 20k
. During a conversion, an external
reference at REFADJ must deliver at least 100A and
have an output impedance less than 100
. The
MAX1146/MAX1148 reference buffer has a 3.277V/V
gain and the MAX1147/MAX1149 has a gain of
2.000V/V. The external reference voltage at REFADJ
multiplied by the reference buffer gain is the SAR ADC
reference voltage. This reference appears at REF and
must be from 1.5V to VDD + 50mV. Bypass REFADJ
with a 0.01F capacitor and bypass REF with a 2.2F
capacitor to AGND.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Output data coding for the MAX1146–MAX1149 is bina-
ry in unipolar mode and two’s complement binary in
bipolar mode with 1 LSB = (VREF/2N), where N is the
number of bits (14). Code transitions occur halfway
between successive-integer LSB values. Figure 14 and
Figure 15 show the input/output (I/O) transfer functions
for unipolar and bipolar operations, respectively.
Serial Interfaces
The MAX1146–MAX1149 feature a serial interface that
is fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU’s serial
interface as a master, so that the CPU generates the
serial clock for the ADCs. Select a clock frequency up
to 2.1MHz.
SPI and MICROWIRE Interface
When using an SPI (Figure 16a) or MICROWIRE interface
(Figure 16b), set CPOL = CPHA = 0. Two 8-bit readings
are necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
MAX1146–
MAX1149
MAX6163
1.250V
BANDGAP
REFERENCE
20k
SAR
ADC
REF
REFERENCE
BUFFER
DISABLED
DGND
VDD
0.1
F
0.1
F
+5V
OUT
IN
GND
+5V
3.000V
AGND
REFADJ
REF
Figure 12. External Reference Applied to REF
MAX1146–
MAX1149
0.047
F
510k
24k
100k
+3.3V
REFADJ
Figure 13. Reference Adjust Circuit
UNIPOLAR MODE
BIPOLAR MODE
INPUT AND OUTPUT
MODES
ZERO SCALE
FULL SCALE
NEGATIVE FULL
SCALE
ZERO SCALE
POSITIVE FULL
SCALE
Single-Ended Mode
VCOM
VREF + VCOM
VCOM
Differential Mode
VIN-
VREF + VIN-
VIN-
Table 7. Full Scale and Zero Scale
Note: The common mode range for the analog inputs is from AGND to VDD.
+
V
REF
COM
2
+
V
REF
IN
2
+
V
REF
COM
2
+
V
REF
IN
2
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