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参数资料
| 型号： | MAX1148BEUP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 116KSPS 20-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 14 |
| 采样率（每秒）： | 116k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 879mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
16
______________________________________________________________________________________
Digital Output
In unipolar input mode, the digital output is straight
binary (Figure 14). For bipolar input mode, the digital
output is two’s complement binary (Figure 15). Data is
clocked out on the falling edge of SCLK in MSB-first
format.
Clock Modes
The MAX1146–MAX1149 can use either the external
serial clock or the internal clock to drive the succes-
sive-approximation conversion. The external clock
shifts data in and out of the MAX1146–MAX1149.
External clock mode allows the fastest throughput rate
(116ksps) and serial clock frequencies from 0.1MHz to
2.1MHz. Internal clock mode provides the best noise
performance because the digital interface can be idle
during conversion. The internal clock mode serial clock
frequency can range from 0 to 2.1MHz. Internal clock
mode allows the CPU to request a conversion and
clock back the results.
Bits PD1 and PD0 of the control byte program the clock
and power-down modes. The MAX1146–MAX1149 power
up in internal clock mode with all circuits activated.
Figures 8–11 illustrate the available clocking modes.
External Clock
In external clock mode, the external clock not only
shifts data in and out, but it also drives the analog-to-
digital conversion. SSTRB pulses high for two clock
periods after the last bit of the control byte. Successive-
approximation bit decisions are made and the results
appear at DOUT on each of the next 14 SCLK falling
edges (Figures 8 and10). SSTRB and DOUT go into a
high-impedance state when CS is high.
Use internal clock mode if the serial clock frequency is
less than 100kHz or if serial clock interruptions could
cause the conversion interval to exceed 140s. The
conversion must complete in 140s, or droop on the
T/H capacitors can degrade conversion results.
Internal Clock
When configured for internal clock mode, the
MAX1146–MAX1149 generate an internal conversion
clock. This frees the P from the burden of running the
SAR conversion clock and allows the conversion results
to be read back at the processor’s convenience, at any
clock rate up to 2.1MHz. SSTRB goes low at the start of
the conversion and then goes high when the conver-
sion is complete. SSTRB is low for a maximum of 8.0s,
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is in
progress. SCLK clocks the data out of this register at any
time after the conversion is complete. After SSTRB goes
high, the second falling SCLK clock edge produces the
MSB of the conversion at DOUT, followed by the remain-
ing bits in MSB-first format (Figures 9 and 11).
For the most accurate conversion, the MAX1146–
MAX1149 digital I/O should remain inactive during the
internal clock conversion interval (tCONV). Do not pull
CS high during conversion. Pulling CS high aborts the
current conversion. To ensure that the next start bit is
recognized, clock in 18 zeros at DIN. When internal
clock mode is selected, SSTRB does not go into a high-
impedance state when CS goes high. A rising edge on
SSTRB indicates that the MAX1146–MAX1149 have fin-
ished the conversion. The P can then read the conver-
sion results at its convenience.
SCLK
SSTRB
DIN
START SEL2
SEL1
SEL0
PD1
PD0
HIGH-Z
18
9
16
24
INPUT MUX
INPUT T/H
SET ACCORDING TO PREVIOUS CONTROL BYTE
SET TO CB1
TRACK
HOLD
HIGH-Z
DOUT
tACQ
HIGH-Z
tCONV
CB1
OPEN
RESET TO CB1
D13
D12
D11
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
D7
CS
SGL/DIF UNI/BIP
Figure 8. External Clock Mode—24 Clocks/Conversion Timing
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相关代理商/技术参数 |
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| MAX1148CGP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1148CUP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1148EGP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1148EUP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1149 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Multichannel, True-Differential, Serial, 14-Bit ADCs |
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