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参数资料
| 型号： | MAX1148BEUP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 116KSPS 20-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 14 |
| 采样率（每秒）： | 116k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 879mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________
11
PIN
MAX1148
MAX1149
MAX1146
MAX1147
NAME
FUNCTION
1
CH0
2
CH1
3
CH2
4
CH3
5
—
CH4
6
—
CH5
7
—
CH6
8
—
CH7
Analog Inputs
9
COM
Common Input. Negative analog input in single-ended mode. COM sets zero-code voltage in
unipolar and bipolar mode.
10
SHDN
Active-Low Shutdown Input. Pulling SHDN low shuts down the device reducing supply current
to 0.2A. Driving shutdown high enables the devices.
11
REF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital
conversion. In internal reference mode, the MAX1146/MAX1148 VREF is +4.096V, and the
MAX1147/MAX1149 VREF is +2.500V.
12
REFADJ
Bandgap Reference Output and Reference Buffer Input. Bypass to AGND with a 0.01F
capacitor. Connect REFADJ to VDD to disable the internal bandgap reference and reference-
buffer amplifier.
13
AGND
Analog Ground
14
DGND
Digital Ground
15
DOUT
Serial Data Output. Data is clocked out at the falling edge of SCLK when CS is low. DOUT is
high impedance when CS is high.
16
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC conversion
begins, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for two clock periods before the MSB decision. SSTRB is high impedance when CS is high
(external clock mode).
17
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK when CS is low. DIN is high
impedance when CS is high.
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
19
SCLK
Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed
in external clock mode. (Duty cycle must be 40% to 60%.)
20
VDD
Positive Supply Voltage. Bypass to AGND with a 0.1F capacitor.
—
5–8
N.C.
No Connection. Not internally connected.
Pin Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1148CGP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1148CUP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1148EGP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1148EUP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1149 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Multichannel, True-Differential, Serial, 14-Bit ADCs |
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