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参数资料
| 型号： | MAX15003ATM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/31页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 48TQFN-EP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 3 |
| 频率 - 最大： | 2.2MHz |
| 电源电压： | 5.5 V ~ 23 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
Pin Description (continued)
PIN
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NAME
FB1
PGOOD1
PGND2
DL2
DREG2
LX2
DH2
BST2
CSN2
CSP2
ILIM2
COMP2
EN/TRACK2
FB2
PGOOD2
PGOOD3
FB3
FUNCTION
Controller 1 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter
output to SGND to set the output voltage. The FB1 voltage regulates to V FB (0.6V).
Controller 1 Power-Good Output. Open-drain PGOOD1 output goes high impedance (releases) when FB1 is
above 0.925 x V FB = 0.555V.
Controller 2 Power Ground Connection. Connect the input filter capacitor’s negative terminal, the source of
the synchronous MOSFET, and the output filter capacitor’s return to PGND2. Connect externally to SGND at
a single point near the input capacitor return terminal.
Controller 2 Low-Side Gate Driver Output. DL2 is the gate driver output for the synchronous MOSFET.
Controller 2 Low-Side Gate Driver Supply. Connect externally to REG and the anode of the boost diode.
Connect at minimum, a 0.1μF ceramic capacitor from DREG2 to PGND2.
Controller 2 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the
inductor and the negative side of the boost capacitor to LX2.
Controller 2 High-Side Gate Driver Output. DH2 drives the gate of the high-side MOSFET.
Controller 2 High-Side Gate Driver Supply. Connect BST2 to the cathode of the boost diode and to the
positive terminal of the boost capacitor.
Controller 2 Negative Current-Sense Input. Connect CSN2 to the synchronous MOSFET drain (connected to
LX2). When using a current-sense resistor, connect CSN2 to the junction of the low-side MOSFET’s source
and the current-sense resistor. See Figure 11.
Controller 2 Positive Current-Sense Input. Connect CSP2 to the synchronous MOSFET source (connected to
PGND2). When using a current-sense resistor, connect CSP2 to the PGND2 end of the current-sense
resistor.
Controller 2 Valley Current-Limit Set Output. Connect a 25k ? to 150k ? resistor, R ILIM2 , from ILIM2 to SGND
to program the valley current-limit threshold from 50mV to 300mV. ILIM2 sources 20μA out to R ILIM2 . The
resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense
resistor, connect a resistive divider from REG to ILIM2 to SGND to set the valley current limit. See Figure 11.
Controller 2 Error Transconductance Amplifier Output. Connect COMP2 to the compensation feedback
network.
Controller 2 Enable/Tracking Input. See Figure 2.
When sequencing, EN/TRACK2 must be above 1.24V for the PWM controller 2 to start.
Coincident tracking—connect the same resistive divider used for FB2, from Output 1 to EN/TRACK2 to
SGND.
Ratiometric tracking—connect EN/TRACK2 to analog ground.
Controller 2 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter
output to SGND to set the output voltage. The FB2 voltage regulates to V FB (0.6V).
Controller 2 Power-Good Output. Open-drain PGOOD2 output goes high impedance (releases) when FB2 is
above 0.925 x V FB = 0.555V.
Controller 3 Power-Good Output. Open-drain PGOOD3 output goes high impedance (releases) when FB3 is
above 0.925 x V FB = 0.555V.
Controller 3 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter
output to SGND to set the output voltage. The FB3 voltage regulates to V FB (0.6V).
Maxim Integrated
11
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